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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
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#include "hal/soc/soc.h"
#include <aos/kernel.h>
/* Logic partition on flash devices */
hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX];
void board_init(void)
{
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_description = "Bootloader";
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_start_addr = 0x08000000;
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_length = 0x8000; //500k bytes
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS;
hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_APPLICATION].partition_description = "Application";
hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = 0x08008000;
hal_partitions[HAL_PARTITION_APPLICATION].partition_length = 0x98000; //608K bytes
hal_partitions[HAL_PARTITION_APPLICATION].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_owner = HAL_FLASH_QSPI;
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_description = "RF Firmware";
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_start_addr = 0x2000;
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_length = 0x3E000; // 4k bytes
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = HAL_FLASH_QSPI;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = "PARAMETER1";
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = 0x0;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = 0x2000; // 8k bytes
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = HAL_FLASH_QSPI;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = "PARAMETER2";
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = 0xDA000;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = 0x2000; //8k bytes
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_description = "OTA Storage";
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_start_addr = 0x40000;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_length = 0x98000; //608K bytes
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_owner = HAL_FLASH_QSPI;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_description = "PARAMETER3";
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_start_addr = 0xD8000;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_owner = HAL_FLASH_QSPI;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_description = "PARAMETER4";
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_start_addr = 0xD9000;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
}
#include "platform_config.h"
#include "platform_peripheral.h"
#include "platform_config.h"
#include "platform_logging.h"
#include "wlan_platform_common.h"
/******************************************************
* Function Declarations
******************************************************/
extern WEAK void PlatformEasyLinkButtonClickedCallback(void);
extern WEAK void PlatformEasyLinkButtonLongPressedCallback(void);
extern WEAK void bootloader_start(void);
/******************************************************
* Variables Definitions
******************************************************/
const platform_gpio_t platform_gpio_pins[] =
{
/* Common GPIOs for internal use */
[FLASH_PIN_QSPI_CS ] = { GPIOC, 11 },
[FLASH_PIN_QSPI_CLK] = { GPIOB, 1 },
[FLASH_PIN_QSPI_D0] = { GPIOA, 6 },
[FLASH_PIN_QSPI_D1] = { GPIOA, 7 },
[FLASH_PIN_QSPI_D2] = { GPIOC, 4 },
[FLASH_PIN_QSPI_D3] = { GPIOC, 5 },
/* GPIOs for external use */
[MICO_GPIO_2] = { GPIOB, 2 },
[MICO_GPIO_4] = { GPIOB, 15 },
[MICO_GPIO_5] = { GPIOB, 12 },
[MICO_GPIO_6] = { GPIOB, 13 },
[MICO_GPIO_7] = { GPIOB, 14 },
[MICO_GPIO_8] = { GPIOC, 6 },
[MICO_GPIO_9] = { GPIOA, 15 },
[MICO_GPIO_12] = { GPIOC, 7 },
[MICO_GPIO_14] = { GPIOC, 0 },
[MICO_GPIO_16] = { GPIOC, 13 },
[MICO_GPIO_17] = { GPIOB, 8 },
[MICO_GPIO_18] = { GPIOB, 9 },
[MICO_GPIO_19] = { GPIOB, 10 },
[MICO_GPIO_27] = { GPIOB, 3 },
[MICO_GPIO_29] = { GPIOB, 7 },
[MICO_GPIO_30] = { GPIOB, 6 },
[MICO_GPIO_31] = { GPIOB, 4 },
[MICO_GPIO_33] = { GPIOA, 10 },
[MICO_GPIO_34] = { GPIOA, 5 },
[MICO_GPIO_35] = { GPIOA, 11 },
[MICO_GPIO_36] = { GPIOA, 12 },
[MICO_GPIO_37] = { GPIOB, 0 },
[MICO_GPIO_38] = { GPIOA, 4 },
};
const platform_pwm_t *platform_pwm_peripherals = NULL;
const platform_i2c_t platform_i2c_peripherals[] =
{
[MICO_I2C_1] =
{
.port = I2C1,
.pin_scl = &platform_gpio_pins[MICO_GPIO_17],
.pin_sda = &platform_gpio_pins[MICO_GPIO_18],
.peripheral_clock_reg = RCC_APB1Periph_I2C1,
.tx_dma = DMA1,
.tx_dma_peripheral_clock = RCC_AHB1Periph_DMA1,
.tx_dma_stream = DMA1_Stream7,
.rx_dma_stream = DMA1_Stream5,
.tx_dma_stream_id = 7,
.rx_dma_stream_id = 5,
.tx_dma_channel = DMA_Channel_1,
.rx_dma_channel = DMA_Channel_1,
.gpio_af_scl = GPIO_AF_I2C1,
.gpio_af_sda = GPIO_AF_I2C1
},
};
platform_i2c_driver_t platform_i2c_drivers[MICO_I2C_MAX];
const platform_uart_t platform_uart_peripherals[] =
{
[MICO_UART_1] =
{
.port = USART6,
.pin_tx = &platform_gpio_pins[MICO_GPIO_8],
.pin_rx = &platform_gpio_pins[MICO_GPIO_12],
.pin_cts = NULL,
.pin_rts = NULL,
.tx_dma_config =
{
.controller = DMA2,
.stream = DMA2_Stream6,
.channel = DMA_Channel_5,
.irq_vector = DMA2_Stream6_IRQn,
.complete_flags = DMA_HISR_TCIF6,
.error_flags = ( DMA_HISR_TEIF6 | DMA_HISR_FEIF6 ),
},
.rx_dma_config =
{
.controller = DMA2,
.stream = DMA2_Stream1,
.channel = DMA_Channel_5,
.irq_vector = DMA2_Stream1_IRQn,
.complete_flags = DMA_LISR_TCIF1,
.error_flags = ( DMA_LISR_TEIF1 | DMA_LISR_FEIF1 | DMA_LISR_DMEIF1 ),
},
},
[MICO_UART_2] =
{
.port = USART1,
.pin_tx = &platform_gpio_pins[MICO_GPIO_30],
.pin_rx = &platform_gpio_pins[MICO_GPIO_29],
.pin_cts = NULL,
.pin_rts = NULL,
.tx_dma_config =
{
.controller = DMA2,
.stream = DMA2_Stream7,
.channel = DMA_Channel_4,
.irq_vector = DMA2_Stream7_IRQn,
.complete_flags = DMA_HISR_TCIF7,
.error_flags = ( DMA_HISR_TEIF7 | DMA_HISR_FEIF7 ),
},
.rx_dma_config =
{
.controller = DMA2,
.stream = DMA2_Stream2,
.channel = DMA_Channel_4,
.irq_vector = DMA2_Stream2_IRQn,
.complete_flags = DMA_LISR_TCIF2,
.error_flags = ( DMA_LISR_TEIF2 | DMA_LISR_FEIF2 | DMA_LISR_DMEIF2 ),
},
},
};
platform_uart_driver_t platform_uart_drivers[MICO_UART_MAX];
const platform_spi_t platform_spi_peripherals[] =
{
[MICO_SPI_1] =
{
.port = SPI2,
.gpio_af = GPIO_AF_SPI2,
.peripheral_clock_reg = RCC_APB1Periph_SPI2,
.peripheral_clock_func = RCC_APB1PeriphClockCmd,
.pin_mosi = &platform_gpio_pins[MICO_GPIO_4],
.pin_miso = &platform_gpio_pins[MICO_GPIO_7],
.pin_clock = &platform_gpio_pins[MICO_GPIO_6],
.tx_dma =
{
.controller = DMA1,
.stream = DMA1_Stream4,
.channel = DMA_Channel_0,
.irq_vector = DMA1_Stream4_IRQn,
.complete_flags = DMA_HISR_TCIF4,
.error_flags = ( DMA_HISR_TEIF4 | DMA_HISR_FEIF4 ),
},
.rx_dma =
{
.controller = DMA1,
.stream = DMA1_Stream3,
.channel = DMA_Channel_0,
.irq_vector = DMA1_Stream3_IRQn,
.complete_flags = DMA_LISR_TCIF3,
.error_flags = ( DMA_LISR_TEIF3 | DMA_LISR_FEIF3 | DMA_LISR_DMEIF3 ),
},
}
};
platform_spi_driver_t platform_spi_drivers[MICO_SPI_MAX];
const platform_qspi_t platform_qspi_peripherals[] =
{
[MICO_QSPI_1] =
{
.port = QUADSPI,
.FSelect = QSPI_FSelect_2,
.peripheral_clock_reg = RCC_AHB3Periph_QSPI,
.peripheral_clock_func = RCC_AHB3PeriphClockCmd,
.pin_d0 = &platform_gpio_pins[FLASH_PIN_QSPI_D0],
.pin_d1 = &platform_gpio_pins[FLASH_PIN_QSPI_D1],
.pin_d2 = &platform_gpio_pins[FLASH_PIN_QSPI_D2],
.pin_d3 = &platform_gpio_pins[FLASH_PIN_QSPI_D3],
.pin_clock = &platform_gpio_pins[FLASH_PIN_QSPI_CLK],
.pin_cs = &platform_gpio_pins[FLASH_PIN_QSPI_CS],
#ifdef USE_QUAD_SPI_DMA
.dma =
{
.controller = DMA2,
.stream = DMA2_Stream7,
.channel = DMA_Channel_3,
.complete_flags = DMA_FLAG_TCIF7,
},
#endif
.gpio_af_d0 = GPIO_AF10_QUADSPI,
.gpio_af_d1 = GPIO_AF10_QUADSPI,
.gpio_af_d2 = GPIO_AF10_QUADSPI,
.gpio_af_d3 = GPIO_AF10_QUADSPI,
.gpio_af_clk = GPIO_AF9_QUADSPI,
.gpio_af_cs = GPIO_AF9_QUADSPI,
}
};
//platform_qspi_driver_t platform_qspi_drivers[MICO_QSPI_MAX];
/* Flash memory devices */
const platform_flash_t platform_flash_peripherals[] =
{
[HAL_FLASH_EMBEDDED] =
{
.flash_type = FLASH_TYPE_EMBEDDED,
.flash_start_addr = 0x08000000,
.flash_length = 0x100000,
},
[HAL_FLASH_QSPI] =
{
.flash_type = FLASH_TYPE_QSPI,
.flash_start_addr = 0x000000,
.flash_length = 0x200000,
},
};
platform_flash_driver_t platform_flash_drivers[HAL_FLASH_MAX];
#if defined ( USE_MICO_SPI_FLASH )
const mico_spi_device_t mico_spi_flash =
{
.port = MICO_SPI_1,
.chip_select = FLASH_PIN_SPI_CS,
.speed = 40000000,
.mode = (SPI_CLOCK_RISING_EDGE | SPI_CLOCK_IDLE_HIGH | SPI_USE_DMA | SPI_MSB_FIRST ),
.bits = 8
};
#endif
const platform_adc_t platform_adc_peripherals[] =
{
[MICO_ADC_1] = { ADC1, ADC_Channel_4, RCC_APB2Periph_ADC1, 1, (platform_gpio_t*)&platform_gpio_pins[MICO_GPIO_38] },
[MICO_ADC_2] = { ADC1, ADC_Channel_5, RCC_APB2Periph_ADC1, 1, (platform_gpio_t*)&platform_gpio_pins[MICO_GPIO_34] },
};
/* Wi-Fi control pins. Used by platform/MCU/wlan_platform_common.c
* SDIO: EMW1062_PIN_BOOTSTRAP[1:0] = b'00
* gSPI: EMW1062_PIN_BOOTSTRAP[1:0] = b'01
*/
const platform_gpio_t wifi_control_pins[] =
{
[WIFI_PIN_RESET] = { GPIOA, 9 },
[WIFI_PIN_32K_CLK] = { GPIOA, 8 },
};
/* Wi-Fi SDIO bus pins. Used by platform/MCU/STM32F2xx/EMW1062_driver/wlan_SDIO.c */
const platform_gpio_t wifi_sdio_pins[] =
{
[WIFI_PIN_SDIO_OOB_IRQ] = { GPIOC, 0 },
[WIFI_PIN_SDIO_CLK ] = { GPIOC, 12 },
[WIFI_PIN_SDIO_CMD ] = { GPIOD, 2 },
[WIFI_PIN_SDIO_D0 ] = { GPIOC, 8 },
[WIFI_PIN_SDIO_D1 ] = { GPIOC, 9 },
[WIFI_PIN_SDIO_D2 ] = { GPIOC, 10 },
[WIFI_PIN_SDIO_D3 ] = { GPIOB, 5 },
};
/******************************************************
* Interrupt Handler Definitions
******************************************************/
MICO_RTOS_DEFINE_ISR( USART1_IRQHandler )
{
platform_uart_irq( &platform_uart_drivers[MICO_UART_2] );
}
MICO_RTOS_DEFINE_ISR( USART6_IRQHandler )
{
platform_uart_irq( &platform_uart_drivers[MICO_UART_1] );
}
MICO_RTOS_DEFINE_ISR( DMA2_Stream6_IRQHandler )
{
platform_uart_tx_dma_irq( &platform_uart_drivers[MICO_UART_1] );
}
MICO_RTOS_DEFINE_ISR( DMA2_Stream7_IRQHandler )
{
platform_uart_tx_dma_irq( &platform_uart_drivers[MICO_UART_2] );
}
MICO_RTOS_DEFINE_ISR( DMA2_Stream1_IRQHandler )
{
platform_uart_rx_dma_irq( &platform_uart_drivers[MICO_UART_1] );
}
MICO_RTOS_DEFINE_ISR( DMA2_Stream2_IRQHandler )
{
platform_uart_rx_dma_irq( &platform_uart_drivers[MICO_UART_2] );
}
/******************************************************
* Function Definitions
******************************************************/
void platform_init_peripheral_irq_priorities( void )
{
/* Interrupt priority setup. Called by MiCO/platform/MCU/STM32F4xx/platform_init.c */
NVIC_SetPriority( RTC_WKUP_IRQn , 1 ); /* RTC Wake-up event */
NVIC_SetPriority( SDIO_IRQn , 2 ); /* WLAN SDIO */
NVIC_SetPriority( DMA2_Stream3_IRQn, 3 ); /* WLAN SDIO DMA */
//NVIC_SetPriority( DMA1_Stream3_IRQn, 3 ); /* WLAN SPI DMA */
NVIC_SetPriority( USART6_IRQn , 6 ); /* MICO_UART_1 */
NVIC_SetPriority( USART1_IRQn , 6 ); /* MICO_UART_2 */
NVIC_SetPriority( DMA2_Stream6_IRQn, 7 ); /* MICO_UART_1 TX DMA */
NVIC_SetPriority( DMA2_Stream1_IRQn, 7 ); /* MICO_UART_1 RX DMA */
NVIC_SetPriority( DMA2_Stream7_IRQn, 7 ); /* MICO_UART_2 TX DMA */
NVIC_SetPriority( DMA2_Stream2_IRQn, 7 ); /* MICO_UART_2 RX DMA */
NVIC_SetPriority( EXTI0_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI1_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI2_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI3_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI4_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI9_5_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI15_10_IRQn , 14 ); /* GPIO */
}
void init_platform( void )
{
}

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#pragma once
#define HARDWARE_REVISION "V1.0"
#define MODEL "STM32F412"
#ifdef BOOTLOADER
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#else
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#endif
#define HSE_SOURCE RCC_HSE_ON /* Use external crystal */
#define AHB_CLOCK_DIVIDER RCC_SYSCLK_Div1 /* AHB clock = System clock */
#define APB1_CLOCK_DIVIDER RCC_HCLK_Div2 /* APB1 clock = AHB clock / 2 */
#define APB2_CLOCK_DIVIDER RCC_HCLK_Div1 /* APB2 clock = AHB clock / 1 */
#define PLL_SOURCE RCC_PLLSource_HSE /* PLL source = external crystal */
#define PLL_M_CONSTANT 13 /* PLLM = 16 */
#define PLL_N_CONSTANT 192 /* PLLN = 400 */
#define PLL_P_CONSTANT 4 /* PLLP = 4 */
#define PPL_Q_CONSTANT 8 /* PLLQ = 8 */
#define PPL_R_CONSTANT 2 /* PLLR = 2 */
#define SYSTEM_CLOCK_SOURCE RCC_SYSCLKSource_PLLCLK /* System clock source = PLL clock */
#define SYSTICK_CLOCK_SOURCE SysTick_CLKSource_HCLK /* SysTick clock source = AHB clock */
#define INT_FLASH_WAIT_STATE FLASH_Latency_3 /* Internal flash wait state = 3 cycles */
#define PWR_WakeUp_Pin PWR_WakeUp_Pin2 /* PWR_Wake_Up_Pin */
/* Wi-Fi chip module */
#define EMW1062
/* GPIO pins are used to bootstrap Wi-Fi to SDIO or gSPI mode */
//#define MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP_0
//#define MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP_1
/* Wi-Fi GPIO0 pin is used for out-of-band interrupt */
#define MICO_WIFI_OOB_IRQ_GPIO_PIN ( 0 )
/* Wi-Fi power pin is present */
//#define MICO_USE_WIFI_POWER_PIN
/* Wi-Fi reset pin is present */
#define MICO_USE_WIFI_RESET_PIN
/* Wi-Fi 32K pin is present */
#define MICO_USE_WIFI_32K_PIN
/*
EMW3166 on EMB-3166-A platform pin definitions ...
+-------------------------------------------------------------------------+
| Enum ID |Pin | STM32| Peripheral | Board | Peripheral |
| | # | Port | Available | Connection | Alias |
|---------------+----+------+-------------+--------------+----------------|
| | 1 | NC | | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_2 | 2 | B 2 | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| | 3 | NC | | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_4 | 4 | B 15 | TIM1_CH3N | | |
| | | | TIM8_CH3N | | |
| | | | SPI2_MOSI | | |
| | | | SDIO_CK | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_5 | 5 | B 12 | SPI2_NSS | | |
| | | | SPI4_NSS | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_6 | 6 | B 13 | TIM1_CH1N | | |
| | | | GPIO | | |
| | | | SPI2_SCK | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_7 | 7 | B 14 | GPIO | | |
| | | | SDIO_D6 | | |
| | | | TIM1_CH2N | | |
| | | | SPI2_MISO | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_8 | 8 | C 6 | TIM3_CH1 | STDIO_UART_TX| MICO_UART_1_TX |
| | | | TIM8_CH1 | | |
| | | | USART6_TX | | |
| | | | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_9 | 9 | A 15 | TIM2_CH1 |EasyLink_BUTTON| |
| | | | JTDI | | |
| | | | USART1_TX | | |
| | | | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| | 10 | VBAT | |
|---------------+----+------+-------------+--------------+----------------|
| | 11 | NC | | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_12 | 12 | C 7 | TIM3_CH2 | STDIO_UART_RX| MICO_UART_1_RX |
| | | | TIM8_CH2 | | |
| | | | SPI2_SCK | | |
| | | | SDIO_D7 | | |
| | | | USART6_RX | | |
| | | | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| | 13 | NRST | | | MICRO_RST_N |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_14 | 14 | C 0 | WAKE_UP | | |
|---------------+----+------+-------------+--------------+----------------|
| | 15 | NC | | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_16 | 16 | C 13 | - | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_SYS_LED | 17 | B 8 | TIM4_CH3 | | |
| | | | I2C2_SCL | | |
| | | | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_18 | 18 | B 9 | TIM4_CH3 | | |
| | | | TIM10_CH1 | | |
| | | | I2C1_SCL | | |
| | | | SDIO_D4 | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_19 | 19 | B 10 | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| | 20 | GND | | | |
+---------------+----+--------------------+--------------+----------------+
| | 21 | GND | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_22 | 22 | B 3 | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_23 | 23 | A 15 | GPIO | | JTAG_TDI |
| | | | USART1_TX | | SPI1_SSN |
| | | | TIM2_CH1 | | |
| | | | TIM2_ETR | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_24 | 24 | B 4 | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_25 | 25 | A 14 | JTCK-SWCLK | SWCLK | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
|MICO_GPIO_26 | 26 | A 13 | JTMS-SWDIO | SWDIO | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
|MICO_GPIO_27 | 27 | B 3 | TIM1_ETR | | |
| | | | USART1_RX | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| | 28 | NC | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_29 | 29 | B 7 | GPIO | | MICO_UART_2_RX |
| | | | TIM4_CH2 | | |
| | | | USART1_RX | | |
| | | | I2C1_SDA | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_30 | 30 | B 6 | GPIO | | MICO_UART_2_TX |
| | | | TIM4_CH1 | | |
| | | | USART1_TX | | |
| | | | I2C1_SCL | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_31 | 31 | B 4 | GPIO | MICO_RF_LED | |
| | | | TIM3_CH1 | | |
| | | | SDIO_D0 | | |
+---------------+----+--------------------+--------------+----------------+
| | 32 | NC | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_33 | 33 | A 10 | TIM1_CH3 | MICO_SYS_LED | |
| | | | SPI5_MOSI | | |
| | | | USB_FS_ID | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_34 | 34 | A 12 | TIM1_ETR | | |
| | | | USART1_RTS | | |
| | | | USB_FS_DP | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_35 | 35 | A 11 | TIM1_CH4 | | |
| | | | SPI4_MISO | | |
| | | | USART1_CTS | | |
| | | | USART6_TX | | |
| | | | USB_FS_DM | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_36 | 36 | A 5 | TIM2_CH1 | BOOT_SEL | |
| | | | TIM2_ETR | | |
| | | | TIM8_CH1N | | |
| | | | SPI1_SCK | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_37 | 37 | B 0 | TIM1_CH2N | MFG_SEL | |
| | | | TIM3_CH3 | | |
| | | | TIM8_CH2N | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_38 | 38 | A 4 | USART2_CK | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| | 39 | VDD | | | |
+---------------+----+--------------------+--------------+----------------+
| | 40 | VDD | | | |
+---------------+----+--------------------+--------------+----------------+
| | 41 | ANT | | | |
+---------------+----+--------------------+--------------+----------------+
*/
typedef enum
{
FLASH_PIN_QSPI_CS,
FLASH_PIN_QSPI_CLK,
FLASH_PIN_QSPI_D0,
FLASH_PIN_QSPI_D1,
FLASH_PIN_QSPI_D2,
FLASH_PIN_QSPI_D3,
MICO_GPIO_2,
MICO_GPIO_4,
MICO_GPIO_5,
MICO_GPIO_6,
MICO_GPIO_7,
MICO_GPIO_8,
MICO_GPIO_9,
MICO_GPIO_12,
MICO_GPIO_14,
MICO_GPIO_16,
MICO_GPIO_17,
MICO_GPIO_18,
MICO_GPIO_19,
MICO_GPIO_27,
MICO_GPIO_29,
MICO_GPIO_30,
MICO_GPIO_31,
MICO_GPIO_33,
MICO_GPIO_34,
MICO_GPIO_35,
MICO_GPIO_36,
MICO_GPIO_37,
MICO_GPIO_38,
MICO_GPIO_MAX, /* Denotes the total number of GPIO port aliases. Not a valid GPIO alias */
MICO_GPIO_NONE,
} mico_gpio_t;
typedef enum
{
MICO_SPI_1,
MICO_SPI_MAX, /* Denotes the total number of SPI port aliases. Not a valid SPI alias */
MICO_SPI_NONE,
} mico_spi_t;
typedef enum
{
MICO_QSPI_1,
MICO_QSPI_MAX,/* Denotes the total number of QSPI port aliases. Not a valid QSPI alias */
MICO_QSPI_NONE,
}mico_qspi_t;
typedef enum
{
MICO_I2C_1,
MICO_I2C_MAX, /* Denotes the total number of I2C port aliases. Not a valid I2C alias */
MICO_I2C_NONE,
} mico_i2c_t;
typedef enum
{
MICO_IIS_MAX, /* Denotes the total number of IIS port aliases. Not a valid IIS alias */
MICO_IIS_NONE,
} mico_iis_t;
typedef enum
{
MICO_PWM_MAX, /* Denotes the total number of PWM port aliases. Not a valid PWM alias */
MICO_PWM_NONE,
} mico_pwm_t;
typedef enum
{
MICO_ADC_1,
MICO_ADC_2,
MICO_ADC_MAX, /* Denotes the total number of ADC port aliases. Not a valid ADC alias */
MICO_ADC_NONE,
} mico_adc_t;
typedef enum
{
MICO_UART_1,
MICO_UART_2,
MICO_UART_MAX, /* Denotes the total number of UART port aliases. Not a valid UART alias */
MICO_UART_NONE,
} mico_uart_t;
typedef hal_flash_t mico_flash_t;
typedef enum
{
MICO_PARTITION_FILESYS,
MICO_PARTITION_USER_MAX
} mico_user_partition_t;
#ifdef BOOTLOADER
#define STDIO_UART (MICO_UART_2)
#define STDIO_UART_BAUDRATE (921600)
#else
#define STDIO_UART (MICO_UART_1)
#define STDIO_UART_BAUDRATE (115200)
#endif
#define UART_FOR_APP (MICO_UART_2)
#define MFG_TEST (MICO_UART_2)
#define CLI_UART (MICO_UART_1)
/* Components connected to external I/Os*/
//#define USE_MICO_SPI_FLASH
//#define SFLASH_SUPPORT_MACRONIX_PARTS
//#define SFLASH_SUPPORT_SST_PARTS
//#define SFLASH_SUPPORT_WINBOND_PARTS
#define USE_QUAD_SPI_FLASH
//#define USE_QUAD_SPI_DMA
#define BOOT_SEL (MICO_GPIO_36)
#define MFG_SEL (MICO_GPIO_37)
#define EasyLink_BUTTON (MICO_GPIO_9)
#define MICO_SYS_LED (MICO_GPIO_33)
#define MICO_RF_LED (MICO_GPIO_31)
/* Arduino extention connector */
#define Arduino_RXD (MICO_GPIO_29)
#define Arduino_TXD (MICO_GPIO_30)
#define Arduino_D2 (MICO_GPIO_NONE)
#define Arduino_D3 (MICO_GPIO_NONE)
#define Arduino_D4 (MICO_GPIO_19)
#define Arduino_D5 (MICO_GPIO_16)
#define Arduino_D6 (MICO_GPIO_14)
#define Arduino_D7 (MICO_GPIO_NONE)
#define Arduino_D8 (MICO_GPIO_2)
#define Arduino_D9 (MICO_GPIO_27)
#define Arduino_CS (MICO_GPIO_5)
#define Arduino_SI (MICO_GPIO_4)
#define Arduino_SO (MICO_GPIO_7)
#define Arduino_SCK (MICO_GPIO_6)
#define Arduino_SDA (MICO_GPIO_18)
#define Arduino_SCL (MICO_GPIO_17)
#define Arduino_A0 (MICO_ADC_NONE)
#define Arduino_A1 (MICO_ADC_NONE)
#define Arduino_A2 (MICO_ADC_1)
#define Arduino_A3 (MICO_ADC_2)
#define Arduino_A4 (MICO_ADC_NONE)
#define Arduino_A5 (MICO_ADC_NONE)
#define Arduino_I2C (MICO_I2C_1)
#define Arduino_SPI (MICO_SPI_1)
#define Arduino_UART (MICO_UART_2)
#ifdef USE_MiCOKit_EXT
#define MICO_I2C_CP (Arduino_I2C)
#include "micokit_ext_def.h"
#else
#define MICO_I2C_CP (MICO_I2C_NONE)
#endif //USE_MiCOKit_EXT

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Living_SDK/board/mk3166/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 1
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
//#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
//#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 100
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#endif /* CONFIG_H */

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MEMORY
{
BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
APP_FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 1000K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
ERAM (rwx) : ORIGIN = 0, LENGTH = 0
}

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Living_SDK/board/mk3166/mk3166.mk Normal file
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NAME := board_mk3166
JTAG := jlink_swd
$(NAME)_TYPE := kernel
MODULE := 3166
HOST_ARCH := Cortex-M4
HOST_MCU_FAMILY := stm32f4xx
HOST_MCU_VARIANT := STM32F412
SUPPORT_BINS := no
BUS := SDIO
$(NAME)_SOURCES := board.c
$(NAME)_PREBUILT_LIBRARY := MiCO.$(MODULE).$(TOOLCHAIN_NAME).a
GLOBAL_INCLUDES += ./
GLOBAL_DEFINES += HSE_VALUE=26000000
GLOBAL_DEFINES += STDIO_UART=0
GLOBAL_DEFINES += RHINO_CONFIG_TICK_TASK=0 RHINO_CONFIG_WORKQUEUE=0
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_MK3166
CONFIG_SYSINFO_DEVICE_NAME := MK3166
GLOBAL_CFLAGS += -DSYSINFO_OS_VERSION=\"$(CONFIG_SYSINFO_OS_VERSION)\"
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
GLOBAL_LDFLAGS += -L $(SOURCE_ROOT)/board/mk3166
# Global defines
# HSE_VALUE = STM32 crystal frequency = 26MHz (needed to make UART work correctly)
GLOBAL_DEFINES += $$(if $$(NO_CRLF_STDIO_REPLACEMENT),,CRLF_STDIO_REPLACEMENT)
GLOBAL_CFLAGS += -DSTM32F412 -mcpu=cortex-m4 -mthumb -mfloat-abi=soft
WIFI_FIRMWARE_SECTOR_START := 2 #0x2000
FILESYSTEM_IMAGE_SECTOR_START := 256 #0x100000
# Extra build target in mico_standard_targets.mk, include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
EXTRA_TARGET_MAKEFILES += $(MAKEFILES_PATH)/aos_standard_targets.mk
#EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk

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#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "stm32l4xx_hal.h"
#include "stm32l4xx_hal_flash.h"
#define EN_DBG 0
#define KM_FLASH_ADDR_START 0x080FF000
#define KM_FLASH_ADDR_SIZE 0x1000
#define FLASH_BLOCK_LEN FLASH_PAGE_SIZE
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t Addr)
{
uint32_t page = 0;
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
/* Bank 1 */
page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE;
}
else
{
/* Bank 2 */
page = (Addr - (FLASH_BASE + FLASH_BANK_SIZE)) / FLASH_PAGE_SIZE;
}
return page;
}
/**
* @brief Gets the bank of a given address
* @param Addr: Address of the FLASH Memory
* @retval The bank of a given address
*/
static uint32_t GetBank(uint32_t Addr)
{
uint32_t bank = 0;
if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
{
/* No Bank swap */
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
bank = FLASH_BANK_1;
}
else
{
bank = FLASH_BANK_2;
}
}
else
{
/* Bank swap */
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
bank = FLASH_BANK_2;
}
else
{
bank = FLASH_BANK_1;
}
}
return bank;
}
int32_t osa_flash_read(void *addr, void *out, size_t size)
{
#if EN_DBG
printf("flash read addr 0x%08x size 0x%08x\n", (uint32_t)addr, size);
#endif
memcpy(out, addr ,size);
#if EN_DBG
printf("data 0x%02x 0x%02x 0x%02x 0x%02x\n",
*((uint8_t *)out + 0), *((uint8_t *)out + 1),
*((uint8_t *)out + 2), *((uint8_t *)out + 3));
#endif
return 0;
}
int32_t osa_flash_write(void *addr, void *buf, size_t size)
{
uint64_t *p = (uint64_t *)buf;
uint32_t a = (uint32_t)addr;
HAL_StatusTypeDef ret = HAL_OK;
if (0 != ((uint32_t)addr % 8) || 0 != (size % 8)) {
printf("bad param addr 0x%08x size 0x%08x\n",
(unsigned int)addr , (unsigned int)size);
return -1;
}
#if EN_DBG
printf("flash write addr 0x%08x size 0x%08x\n",
(uint32_t)addr , (uint32_t)size);
#endif
HAL_FLASH_Unlock();
while ((size >= 8) && (ret == HAL_OK)) {
ret = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, (uint32_t)a, (uint64_t)(*p));
if (0 != ret) {
printf("write flash fail addr %08x data %llx ret 0x%08x\n",
(unsigned int)a, (uint64_t)(*p), (unsigned int)ret);
return -1;
}
#if EN_DBG
uint8_t tmp_buf[8];
int i;
osa_flash_read((void *)a , tmp_buf, 8);
if (0 != memcmp(tmp_buf, p, 8)) {
printf("write than read not match \n");
for (i = 0; i < 8; ++i) {
printf("write buf 0x%02x read data 0x%02x\n", *((uint8_t *)p + i), tmp_buf[i]);
}
return -1;
}
#if 0
for (i = 0; i < 8; ++i) {
printf("write buf 0x%02x read data 0x%02x\n", *((uint8_t *)p + i), tmp_buf[i]);
}
#endif
#endif
p = (uint64_t *)((uint32_t)p + 8);
a += 8;
size -= 8;
}
HAL_FLASH_Lock();
return 0;
}
int32_t osa_flash_erase(void *addr, size_t size)
{
uint32_t PageError = 0;
FLASH_EraseInitTypeDef pEraseInit;
uint32_t cur_addr = (uint32_t)addr;
size_t cur_size = size;
HAL_FLASH_Unlock();
if (0 != (size % FLASH_BLOCK_LEN) || 0 != (cur_addr % FLASH_BLOCK_LEN)) {
printf("bad param addr 0x%08x size 0x%08x\n",
(unsigned int)addr, (unsigned int)size);
return -1;
}
if (0 == size) {
return 0;
}
while (cur_size > 0) {
/* Fill EraseInit structure*/
pEraseInit.TypeErase = FLASH_TYPEERASE_PAGES;
pEraseInit.Banks = GetBank(cur_addr);
pEraseInit.Page = GetPage(cur_addr);
pEraseInit.NbPages = 1;
#if EN_DBG
printf("flash erase page %d bank %d\n", GetPage(cur_addr), GetBank(cur_addr));
#endif
if (HAL_FLASHEx_Erase(&pEraseInit, &PageError) != HAL_OK)
{
printf("flash erase fail\n");
return -1;
}
cur_size -= FLASH_BLOCK_LEN;
cur_addr -= FLASH_BLOCK_LEN;
}
HAL_FLASH_Lock();
return 0;
}
int32_t getRDPLevel(uint32_t *RDPLevel)
{
FLASH_OBProgramInitTypeDef sFlashOptionBytes;
int32_t eRetStatus = 0;
if (NULL == RDPLevel) {
return -1;
}
/* Unlock the Flash to enable the flash control register access
*************/
HAL_FLASH_Unlock();
/* Clear OPTVERR bit set on virgin samples */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
/* Unlock the Options Bytes
*************************************************/
HAL_FLASH_OB_Unlock();
/* Get Option Bytes status for FLASH_BANK_1: WRP AREA_A and PCRoP
**********/
HAL_FLASHEx_OBGetConfig(&sFlashOptionBytes);
*RDPLevel = sFlashOptionBytes.RDPLevel;
/* Lock the Options Bytes
***************************************************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
return eRetStatus;
}
int32_t ConfigWRP (bool enable, bool reboot)
{
int32_t eRetStatus = 0;
uint32_t RDPlevel;
uint32_t StartPage = 0, EndPage = 0, StartBank = 0, EndBank = 0;
FLASH_OBProgramInitTypeDef psFlashOptionBytes, psFlashOptionBytes2;
eRetStatus = getRDPLevel(&RDPlevel);
if (0 != eRetStatus) {
return -1;
}
if (OB_RDP_LEVEL_2 == RDPlevel) {
return -1;
}
/* Get the number of the start and end pages */
StartPage = GetPage(KM_FLASH_ADDR_START);
EndPage = GetPage(KM_FLASH_ADDR_START + KM_FLASH_ADDR_SIZE - 1);
/* Get the bank of the start and end pages */
StartBank = GetBank(KM_FLASH_ADDR_START);
EndBank = GetBank(KM_FLASH_ADDR_START + KM_FLASH_ADDR_SIZE - 1);
if (StartBank != EndBank) {
/* cross bank not support now */
return -1;
}
/* WRP area is only on one bank */
if (StartBank == FLASH_BANK_1)
{
psFlashOptionBytes.WRPArea = OB_WRPAREA_BANK1_AREAA;
psFlashOptionBytes2.WRPArea = OB_WRPAREA_BANK1_AREAB;
}
else
{
psFlashOptionBytes.WRPArea = OB_WRPAREA_BANK2_AREAA;
psFlashOptionBytes2.WRPArea = OB_WRPAREA_BANK2_AREAB;
}
HAL_FLASH_Unlock();
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
HAL_FLASH_OB_Unlock();
HAL_FLASHEx_OBGetConfig(&psFlashOptionBytes);
HAL_FLASHEx_OBGetConfig(&psFlashOptionBytes2);
if (true == enable) {
/* Check if desired pages are not yet write protected ***********************/
if ((psFlashOptionBytes.WRPStartOffset <= StartPage) && (psFlashOptionBytes.WRPEndOffset >= (StartPage - 1)))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes.WRPEndOffset < EndPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
}
else if ((psFlashOptionBytes.WRPStartOffset <= (EndPage + 1)) && (psFlashOptionBytes.WRPEndOffset >= EndPage))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes.WRPStartOffset > StartPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
}
}
else if ((psFlashOptionBytes.WRPStartOffset > StartPage) && (psFlashOptionBytes.WRPEndOffset < EndPage))
{
/* Current area is included in pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
else if ((psFlashOptionBytes2.WRPStartOffset <= StartPage) && (psFlashOptionBytes2.WRPEndOffset >= (StartPage - 1)))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes2.WRPEndOffset < EndPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset <= (EndPage + 1)) && (psFlashOptionBytes2.WRPEndOffset >= EndPage))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes2.WRPStartOffset > StartPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset > StartPage) && (psFlashOptionBytes2.WRPEndOffset < EndPage))
{
/* Current area is included in pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
else if (psFlashOptionBytes.WRPStartOffset > psFlashOptionBytes.WRPEndOffset)
{
/* Current area is not used => it will be configured to protect the pages */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
else if (psFlashOptionBytes2.WRPStartOffset > psFlashOptionBytes2.WRPEndOffset)
{
/* Current area is not used => it will be configured to protect the pages */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
else
{
/* No more area available to protect the pages */
/* => Error : not possible to activate the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
} else {
/* disable */
/* Check if desired pages are already write protected ***********************/
if ((psFlashOptionBytes.WRPStartOffset == StartPage) && (psFlashOptionBytes.WRPEndOffset == EndPage))
{
/* Current area correspond to the area to disable */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = 0xFF;
psFlashOptionBytes.WRPEndOffset = 0;
}
else if ((psFlashOptionBytes.WRPStartOffset == StartPage) && (psFlashOptionBytes.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable : */
/* - End of area is bigger than the last page to un-protect */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = EndPage + 1;
}
else if ((psFlashOptionBytes.WRPStartOffset < StartPage) && (psFlashOptionBytes.WRPEndOffset == EndPage))
{
/* Current area is bigger than the area to disable : */
/* - Start of area is lower than the first page to un-protect */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = StartPage - 1;
}
else if ((psFlashOptionBytes.WRPStartOffset < StartPage) && (psFlashOptionBytes.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable */
/* - Start of area is lower than the first page to un-protect */
/* - End of area is bigger than the last page to un-protect */
if (psFlashOptionBytes2.WRPStartOffset > psFlashOptionBytes2.WRPEndOffset)
{
/* Second area of the bank can be used */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = EndPage + 1;
psFlashOptionBytes2.WRPEndOffset = psFlashOptionBytes.WRPEndOffset;
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = StartPage - 1;
}
else
{
/* Second area of the bank already used for WRP */
/* => Error : not possible to deactivate only the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset == StartPage) && (psFlashOptionBytes2.WRPEndOffset == EndPage))
{
/* Current area correspond to the area to disable */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = 0xFF;
psFlashOptionBytes2.WRPEndOffset = 0;
}
else if ((psFlashOptionBytes2.WRPStartOffset == StartPage) && (psFlashOptionBytes2.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable : */
/* - End of area is bigger than the last page to un-protect */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = EndPage + 1;
}
else if ((psFlashOptionBytes2.WRPStartOffset < StartPage) && (psFlashOptionBytes2.WRPEndOffset == EndPage))
{
/* Current area is bigger than the area to disable : */
/* - Start of area is lower than the first page to un-protect */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = StartPage - 1;
}
else if ((psFlashOptionBytes2.WRPStartOffset < StartPage) && (psFlashOptionBytes2.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable */
/* - Start of area is lower than the first page to un-protect */
/* - End of area is bigger than the last page to un-protect */
if (psFlashOptionBytes.WRPStartOffset > psFlashOptionBytes.WRPEndOffset)
{
/* Second area of the bank can be used */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = EndPage + 1;
psFlashOptionBytes.WRPEndOffset = psFlashOptionBytes2.WRPEndOffset;
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = StartPage - 1;
}
else
{
/* Second area of the bank already used for WRP */
/* => Error : not possible to deactivate only the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
}
/* Configure write protected pages */
if (psFlashOptionBytes.OptionType == OPTIONBYTE_WRP)
{
if(HAL_FLASHEx_OBProgram(&psFlashOptionBytes) != HAL_OK)
{
/* Error occurred while options bytes programming. **********************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
if (psFlashOptionBytes2.OptionType == OPTIONBYTE_WRP)
{
if(HAL_FLASHEx_OBProgram(&psFlashOptionBytes2) != HAL_OK)
{
/* Error occurred while options bytes programming. **********************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
/* Generate System Reset to load the new option byte values ***************/
if (((psFlashOptionBytes.OptionType == OPTIONBYTE_WRP) || (psFlashOptionBytes2.OptionType == OPTIONBYTE_WRP)) && reboot)
{
HAL_FLASH_OB_Launch();
}
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
return eRetStatus;
}
int32_t CleanProtectionWRP (void)
{
int32_t eRetStatus = 0;
uint32_t RDPlevel;
FLASH_OBProgramInitTypeDef psFlashOptionBytes;
eRetStatus = getRDPLevel(&RDPlevel);
if (0 != eRetStatus) {
return -1;
}
if (OB_RDP_LEVEL_2 == RDPlevel) {
return -1;
}
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPArea = 0;//SFU_HAL_IF_PROTECT_WRP_AREA_1;
psFlashOptionBytes.WRPStartOffset = 0;
psFlashOptionBytes.WRPEndOffset = 0;
if (HAL_FLASHEx_OBProgram(&psFlashOptionBytes) != HAL_OK) {
eRetStatus = -1;
}
return eRetStatus;
}