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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
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#include "hal/soc/soc.h"
#include <aos/kernel.h>
/* Logic partition on flash devices */
hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX];
void board_init(void)
{
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_description = "Bootloader";
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_start_addr = 0x08000000;
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_length = 0x8000; //500k bytes
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS;
hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_APPLICATION].partition_description = "Application";
hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = 0x0800C000;
hal_partitions[HAL_PARTITION_APPLICATION].partition_length = 0x98000; //608K bytes
hal_partitions[HAL_PARTITION_APPLICATION].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_owner = HAL_FLASH_SPI;
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_description = "RF Firmware";
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_start_addr = 0x2000;
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_length = 0x3E000; // 4k bytes
hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = HAL_FLASH_SPI;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = "PARAMETER1";
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = 0x0;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = 0x2000; // 8k bytes
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = HAL_FLASH_SPI;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = "PARAMETER2";
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = 0xDA000;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = 0x2000; //8k bytes
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_owner = HAL_FLASH_SPI;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_description = "OTA Storage";
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_start_addr = 0x40000;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_length = 0x98000; //608K bytes
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_owner = HAL_FLASH_SPI;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_description = "PARAMETER3";
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_start_addr = 0xD8000;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_owner = HAL_FLASH_SPI;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_description = "PARAMETER4";
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_start_addr = 0xD9000;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
}
#include "platform_config.h"
#include "platform_peripheral.h"
#include "platform_config.h"
#include "platform_logging.h"
#include "wlan_platform_common.h"
/******************************************************
* Function Declarations
******************************************************/
extern WEAK void PlatformEasyLinkButtonClickedCallback(void);
extern WEAK void PlatformEasyLinkButtonLongPressedCallback(void);
extern WEAK void bootloader_start(void);
/******************************************************
* Variables Definitions
******************************************************/
const platform_gpio_t platform_gpio_pins[] =
{
/* Common GPIOs for internal use */
[MICO_SYS_LED] = { GPIOB, 13 },
[MICO_RF_LED] = { GPIOB, 8 },
[BOOT_SEL] = { GPIOB, 1 },
[MFG_SEL] = { GPIOB, 0 },
[EasyLink_BUTTON] = { GPIOA, 1 },
[STDIO_UART_RX] = { GPIOA, 3 },
[STDIO_UART_TX] = { GPIOA, 2 },
[FLASH_PIN_SPI_CS ] = { GPIOA, 15 },
[FLASH_PIN_SPI_CLK ] = { GPIOB, 3 },
[FLASH_PIN_SPI_MOSI] = { GPIOA, 7 },
[FLASH_PIN_SPI_MISO] = { GPIOB, 4 },
/* GPIOs for external use */
[MICO_GPIO_2] = { GPIOB, 2 },
[MICO_GPIO_8] = { GPIOA , 2 },
[MICO_GPIO_9] = { GPIOA, 1 },
[MICO_GPIO_12] = { GPIOA, 3 },
[MICO_GPIO_14] = { GPIOA, 0 },
[MICO_GPIO_16] = { GPIOC, 13 },
[MICO_GPIO_17] = { GPIOB, 10 },
[MICO_GPIO_18] = { GPIOB, 9 },
[MICO_GPIO_19] = { GPIOB, 12 },
[MICO_GPIO_27] = { GPIOA, 12 },
[MICO_GPIO_29] = { GPIOA, 10 },
[MICO_GPIO_30] = { GPIOB, 6 },
[MICO_GPIO_31] = { GPIOB, 8 },
[MICO_GPIO_33] = { GPIOB, 13 },
[MICO_GPIO_34] = { GPIOA, 5 },
[MICO_GPIO_35] = { GPIOA, 11 },
[MICO_GPIO_36] = { GPIOB, 1 },
[MICO_GPIO_37] = { GPIOB, 0 },
[MICO_GPIO_38] = { GPIOA, 4 },
};
const platform_pwm_t *platform_pwm_peripherals = NULL;
const platform_i2c_t platform_i2c_peripherals[] =
{
[MICO_I2C_1] =
{
.port = I2C2,
.pin_scl = &platform_gpio_pins[MICO_GPIO_17],
.pin_sda = &platform_gpio_pins[MICO_GPIO_18],
.peripheral_clock_reg = RCC_APB1Periph_I2C2,
.tx_dma = DMA1,
.tx_dma_peripheral_clock = RCC_AHB1Periph_DMA1,
.tx_dma_stream = DMA1_Stream7,
.rx_dma_stream = DMA1_Stream5,
.tx_dma_stream_id = 7,
.rx_dma_stream_id = 5,
.tx_dma_channel = DMA_Channel_1,
.rx_dma_channel = DMA_Channel_1,
.gpio_af_scl = GPIO_AF_I2C2,
.gpio_af_sda = GPIO_AF9_I2C2
},
};
platform_i2c_driver_t platform_i2c_drivers[MICO_I2C_MAX];
const platform_uart_t platform_uart_peripherals[] =
{
[MICO_UART_1] =
{
.port = USART2,
.pin_tx = &platform_gpio_pins[STDIO_UART_TX],
.pin_rx = &platform_gpio_pins[STDIO_UART_RX],
.pin_cts = NULL,
.pin_rts = NULL,
.tx_dma_config =
{
.controller = DMA1,
.stream = DMA1_Stream6,
.channel = DMA_Channel_4,
.irq_vector = DMA1_Stream6_IRQn,
.complete_flags = DMA_HISR_TCIF6,
.error_flags = ( DMA_HISR_TEIF6 | DMA_HISR_FEIF6 ),
},
.rx_dma_config =
{
.controller = DMA1,
.stream = DMA1_Stream5,
.channel = DMA_Channel_4,
.irq_vector = DMA1_Stream5_IRQn,
.complete_flags = DMA_HISR_TCIF5,
.error_flags = ( DMA_HISR_TEIF5 | DMA_HISR_FEIF5 | DMA_HISR_DMEIF5 ),
},
},
[MICO_UART_2] =
{
.port = USART1,
.pin_tx = &platform_gpio_pins[MICO_GPIO_30],
.pin_rx = &platform_gpio_pins[MICO_GPIO_29],
.pin_cts = &platform_gpio_pins[MICO_GPIO_35],
.pin_rts = &platform_gpio_pins[MICO_GPIO_27],
.tx_dma_config =
{
.controller = DMA2,
.stream = DMA2_Stream7,
.channel = DMA_Channel_4,
.irq_vector = DMA2_Stream7_IRQn,
.complete_flags = DMA_HISR_TCIF7,
.error_flags = ( DMA_HISR_TEIF7 | DMA_HISR_FEIF7 ),
},
.rx_dma_config =
{
.controller = DMA2,
.stream = DMA2_Stream2,
.channel = DMA_Channel_4,
.irq_vector = DMA2_Stream2_IRQn,
.complete_flags = DMA_LISR_TCIF2,
.error_flags = ( DMA_LISR_TEIF2 | DMA_LISR_FEIF2 | DMA_LISR_DMEIF2 ),
},
},
};
platform_uart_driver_t platform_uart_drivers[MICO_UART_MAX];
const platform_spi_t platform_spi_peripherals[] =
{
[MICO_SPI_1] =
{
.port = SPI1,
.gpio_af = GPIO_AF_SPI1,
.peripheral_clock_reg = RCC_APB2Periph_SPI1,
.peripheral_clock_func = RCC_APB2PeriphClockCmd,
.pin_mosi = &platform_gpio_pins[FLASH_PIN_SPI_MOSI],
.pin_miso = &platform_gpio_pins[FLASH_PIN_SPI_MISO],
.pin_clock = &platform_gpio_pins[FLASH_PIN_SPI_CLK],
.tx_dma =
{
.controller = DMA2,
.stream = DMA2_Stream5,
.channel = DMA_Channel_3,
.irq_vector = DMA2_Stream5_IRQn,
.complete_flags = DMA_HISR_TCIF5,
.error_flags = ( DMA_HISR_TEIF5 | DMA_HISR_FEIF5 ),
},
.rx_dma =
{
.controller = DMA2,
.stream = DMA2_Stream0,
.channel = DMA_Channel_3,
.irq_vector = DMA2_Stream0_IRQn,
.complete_flags = DMA_LISR_TCIF0,
.error_flags = ( DMA_LISR_TEIF0 | DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 ),
},
}
};
platform_spi_driver_t platform_spi_drivers[MICO_SPI_MAX];
/* Flash memory devices */
const platform_flash_t platform_flash_peripherals[] =
{
[HAL_FLASH_EMBEDDED] =
{
.flash_type = FLASH_TYPE_EMBEDDED,
.flash_start_addr = 0x08000000,
.flash_length = 0x80000,
},
[HAL_FLASH_SPI] =
{
.flash_type = FLASH_TYPE_SPI,
.flash_start_addr = 0x000000,
.flash_length = 0x200000,
},
};
platform_flash_driver_t platform_flash_drivers[HAL_FLASH_MAX];
#if defined ( USE_MICO_SPI_FLASH )
const platforom_spi_device_t mico_spi_flash =
{
.port = MICO_SPI_1,
.chip_select = FLASH_PIN_SPI_CS,
.speed = 40000000,
.mode = (SPI_CLOCK_RISING_EDGE | SPI_CLOCK_IDLE_HIGH | SPI_USE_DMA | SPI_MSB_FIRST ),
.bits = 8
};
#endif
const platform_adc_t platform_adc_peripherals[] =
{
[MICO_ADC_1] = { ADC1, ADC_Channel_4, RCC_APB2Periph_ADC1, 1, (platform_gpio_t*)&platform_gpio_pins[MICO_GPIO_38] },
[MICO_ADC_2] = { ADC1, ADC_Channel_5, RCC_APB2Periph_ADC1, 1, (platform_gpio_t*)&platform_gpio_pins[MICO_GPIO_34] },
};
/* Wi-Fi control pins. Used by platform/MCU/wlan_platform_common.c
* SDIO: EMW1062_PIN_BOOTSTRAP[1:0] = b'00
* gSPI: EMW1062_PIN_BOOTSTRAP[1:0] = b'01
*/
const platform_gpio_t wifi_control_pins[] =
{
[WIFI_PIN_RESET] = { GPIOB, 14 },
};
/* Wi-Fi SDIO bus pins. Used by platform/MCU/STM32F2xx/EMW1062_driver/wlan_SDIO.c */
const platform_gpio_t wifi_sdio_pins[] =
{
[WIFI_PIN_SDIO_OOB_IRQ] = { GPIOA, 0 },
[WIFI_PIN_SDIO_CLK ] = { GPIOB, 15 },
[WIFI_PIN_SDIO_CMD ] = { GPIOA, 6 },
[WIFI_PIN_SDIO_D0 ] = { GPIOB, 7 },
[WIFI_PIN_SDIO_D1 ] = { GPIOA, 8 },
[WIFI_PIN_SDIO_D2 ] = { GPIOA, 9 },
[WIFI_PIN_SDIO_D3 ] = { GPIOB, 5 },
};
/******************************************************
* Interrupt Handler Definitions
******************************************************/
MICO_RTOS_DEFINE_ISR( USART1_IRQHandler )
{
platform_uart_irq( &platform_uart_drivers[MICO_UART_2] );
}
MICO_RTOS_DEFINE_ISR( USART2_IRQHandler )
{
platform_uart_irq( &platform_uart_drivers[MICO_UART_1] );
}
MICO_RTOS_DEFINE_ISR( DMA1_Stream6_IRQHandler )
{
platform_uart_tx_dma_irq( &platform_uart_drivers[MICO_UART_1] );
}
MICO_RTOS_DEFINE_ISR( DMA2_Stream7_IRQHandler )
{
platform_uart_tx_dma_irq( &platform_uart_drivers[MICO_UART_2] );
}
MICO_RTOS_DEFINE_ISR( DMA1_Stream5_IRQHandler )
{
platform_uart_rx_dma_irq( &platform_uart_drivers[MICO_UART_1] );
}
MICO_RTOS_DEFINE_ISR( DMA2_Stream2_IRQHandler )
{
platform_uart_rx_dma_irq( &platform_uart_drivers[MICO_UART_2] );
}
/******************************************************
* Function Definitions
******************************************************/
void platform_init_peripheral_irq_priorities( void )
{
/* Interrupt priority setup. Called by MiCO/platform/MCU/STM32F2xx/platform_init.c */
NVIC_SetPriority( RTC_WKUP_IRQn , 1 ); /* RTC Wake-up event */
NVIC_SetPriority( SDIO_IRQn , 2 ); /* WLAN SDIO */
NVIC_SetPriority( DMA2_Stream3_IRQn, 3 ); /* WLAN SDIO DMA */
//NVIC_SetPriority( DMA1_Stream3_IRQn, 3 ); /* WLAN SPI DMA */
NVIC_SetPriority( USART1_IRQn , 6 ); /* MICO_UART_1 */
NVIC_SetPriority( USART2_IRQn , 6 ); /* MICO_UART_2 */
NVIC_SetPriority( DMA1_Stream6_IRQn, 7 ); /* MICO_UART_1 TX DMA */
NVIC_SetPriority( DMA1_Stream5_IRQn, 7 ); /* MICO_UART_1 RX DMA */
NVIC_SetPriority( DMA2_Stream7_IRQn, 7 ); /* MICO_UART_2 TX DMA */
NVIC_SetPriority( DMA2_Stream2_IRQn, 7 ); /* MICO_UART_2 RX DMA */
NVIC_SetPriority( EXTI0_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI1_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI2_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI3_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI4_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI9_5_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI15_10_IRQn , 14 ); /* GPIO */
}
void init_platform( void )
{
}

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#pragma once
#define HARDWARE_REVISION "V1.0"
#define MODEL "STM32F411"
#ifdef BOOTLOADER
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#else
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#endif
#define HSE_SOURCE RCC_HSE_ON /* Use external crystal */
#define AHB_CLOCK_DIVIDER RCC_SYSCLK_Div1 /* AHB clock = System clock */
#define APB1_CLOCK_DIVIDER RCC_HCLK_Div2 /* APB1 clock = AHB clock / 2 */
#define APB2_CLOCK_DIVIDER RCC_HCLK_Div1 /* APB2 clock = AHB clock / 1 */
#define PLL_SOURCE RCC_PLLSource_HSE /* PLL source = external crystal */
#define PLL_M_CONSTANT 26 /* PLLM = 16 */
#define PLL_N_CONSTANT 400 /* PLLN = 400 */
#define PLL_P_CONSTANT 4 /* PLLP = 4 */
#define PPL_Q_CONSTANT 7 /* PLLQ = 8 */
#define SYSTEM_CLOCK_SOURCE RCC_SYSCLKSource_PLLCLK /* System clock source = PLL clock */
#define SYSTICK_CLOCK_SOURCE SysTick_CLKSource_HCLK /* SysTick clock source = AHB clock */
#define INT_FLASH_WAIT_STATE FLASH_Latency_3 /* Internal flash wait state = 3 cycles */
/* Wi-Fi chip module */
#define EMW1062
/* GPIO pins are used to bootstrap Wi-Fi to SDIO or gSPI mode */
//#define MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP_0
//#define MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP_1
/* Wi-Fi GPIO0 pin is used for out-of-band interrupt */
#define MICO_WIFI_OOB_IRQ_GPIO_PIN ( 0 )
/* Wi-Fi power pin is present */
//#define MICO_USE_WIFI_POWER_PIN
/* Wi-Fi reset pin is present */
#define MICO_USE_WIFI_RESET_PIN
/* Wi-Fi 32K pin is present */
#define MICO_USE_WIFI_32K_PIN
/*
EMW3166 on EMB-3166-A platform pin definitions ...
+-------------------------------------------------------------------------+
| Enum ID |Pin | STM32| Peripheral | Board | Peripheral |
| | # | Port | Available | Connection | Alias |
|---------------+----+------+-------------+--------------+----------------|
| | 1 | NC | | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_2 | 2 | B 2 | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| | 3 | NC | | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_4 | 4 | B 15 | TIM1_CH3N | | |
| | | | TIM8_CH3N | | |
| | | | SPI2_MOSI | | |
| | | | SDIO_CK | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_5 | 5 | B 12 | SPI2_NSS | | |
| | | | SPI4_NSS | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_6 | 6 | B 13 | TIM1_CH1N | | |
| | | | GPIO | | |
| | | | SPI2_SCK | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_7 | 7 | B 14 | GPIO | | |
| | | | SDIO_D6 | | |
| | | | TIM1_CH2N | | |
| | | | SPI2_MISO | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_8 | 8 | C 6 | TIM3_CH1 | STDIO_UART_TX| MICO_UART_1_TX |
| | | | TIM8_CH1 | | |
| | | | USART6_TX | | |
| | | | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_9 | 9 | A 15 | TIM2_CH1 |EasyLink_BUTTON| |
| | | | JTDI | | |
| | | | USART1_TX | | |
| | | | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| | 10 | VBAT | |
|---------------+----+------+-------------+--------------+----------------|
| | 11 | NC | | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_12 | 12 | C 7 | TIM3_CH2 | STDIO_UART_RX| MICO_UART_1_RX |
| | | | TIM8_CH2 | | |
| | | | SPI2_SCK | | |
| | | | SDIO_D7 | | |
| | | | USART6_RX | | |
| | | | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| | 13 | NRST | | | MICRO_RST_N |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_14 | 14 | C 0 | WAKE_UP | | |
|---------------+----+------+-------------+--------------+----------------|
| | 15 | NC | | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_16 | 16 | C 13 | - | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_SYS_LED | 17 | B 8 | TIM4_CH3 | | |
| | | | I2C2_SCL | | |
| | | | GPIO | | |
|---------------+----+------+-------------+--------------+----------------|
| MICO_GPIO_18 | 18 | B 9 | TIM4_CH3 | | |
| | | | TIM10_CH1 | | |
| | | | I2C1_SCL | | |
| | | | SDIO_D4 | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_19 | 19 | B 10 | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| | 20 | GND | | | |
+---------------+----+--------------------+--------------+----------------+
| | 21 | GND | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_22 | 22 | B 3 | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_23 | 23 | A 15 | GPIO | | JTAG_TDI |
| | | | USART1_TX | | SPI1_SSN |
| | | | TIM2_CH1 | | |
| | | | TIM2_ETR | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_24 | 24 | B 4 | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_25 | 25 | A 14 | JTCK-SWCLK | SWCLK | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
|MICO_GPIO_26 | 26 | A 13 | JTMS-SWDIO | SWDIO | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
|MICO_GPIO_27 | 27 | B 3 | TIM1_ETR | | |
| | | | USART1_RX | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| | 28 | NC | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_29 | 29 | B 7 | GPIO | | MICO_UART_2_RX |
| | | | TIM4_CH2 | | |
| | | | USART1_RX | | |
| | | | I2C1_SDA | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_30 | 30 | B 6 | GPIO | | MICO_UART_2_TX |
| | | | TIM4_CH1 | | |
| | | | USART1_TX | | |
| | | | I2C1_SCL | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_31 | 31 | B 4 | GPIO | MICO_RF_LED | |
| | | | TIM3_CH1 | | |
| | | | SDIO_D0 | | |
+---------------+----+--------------------+--------------+----------------+
| | 32 | NC | | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_33 | 33 | A 10 | TIM1_CH3 | MICO_SYS_LED | |
| | | | SPI5_MOSI | | |
| | | | USB_FS_ID | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_34 | 34 | A 12 | TIM1_ETR | | |
| | | | USART1_RTS | | |
| | | | USB_FS_DP | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_35 | 35 | A 11 | TIM1_CH4 | | |
| | | | SPI4_MISO | | |
| | | | USART1_CTS | | |
| | | | USART6_TX | | |
| | | | USB_FS_DM | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_36 | 36 | A 5 | TIM2_CH1 | BOOT_SEL | |
| | | | TIM2_ETR | | |
| | | | TIM8_CH1N | | |
| | | | SPI1_SCK | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_37 | 37 | B 0 | TIM1_CH2N | MFG_SEL | |
| | | | TIM3_CH3 | | |
| | | | TIM8_CH2N | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| MICO_GPIO_38 | 38 | A 4 | USART2_CK | | |
| | | | GPIO | | |
+---------------+----+--------------------+--------------+----------------+
| | 39 | VDD | | | |
+---------------+----+--------------------+--------------+----------------+
| | 40 | VDD | | | |
+---------------+----+--------------------+--------------+----------------+
| | 41 | ANT | | | |
+---------------+----+--------------------+--------------+----------------+
*/
typedef enum
{
MICO_SYS_LED,
MICO_RF_LED,
BOOT_SEL,
MFG_SEL,
EasyLink_BUTTON,
STDIO_UART_RX,
STDIO_UART_TX,
FLASH_PIN_SPI_CS,
FLASH_PIN_SPI_CLK,
FLASH_PIN_SPI_MOSI,
FLASH_PIN_SPI_MISO,
MICO_GPIO_2,
MICO_GPIO_8,
MICO_GPIO_9,
MICO_GPIO_12,
MICO_GPIO_14,
MICO_GPIO_16,
MICO_GPIO_17,
MICO_GPIO_18,
MICO_GPIO_19,
MICO_GPIO_27,
MICO_GPIO_29,
MICO_GPIO_30,
MICO_GPIO_31,
MICO_GPIO_33,
MICO_GPIO_34,
MICO_GPIO_35,
MICO_GPIO_36,
MICO_GPIO_37,
MICO_GPIO_38,
MICO_GPIO_MAX, /* Denotes the total number of GPIO port aliases. Not a valid GPIO alias */
MICO_GPIO_NONE,
} mico_gpio_t;
typedef enum
{
MICO_SPI_1,
MICO_SPI_MAX, /* Denotes the total number of SPI port aliases. Not a valid SPI alias */
MICO_SPI_NONE,
} mico_spi_t;
typedef enum
{
MICO_QSPI_1,
MICO_QSPI_MAX,/* Denotes the total number of QSPI port aliases. Not a valid QSPI alias */
MICO_QSPI_NONE,
}mico_qspi_t;
typedef enum
{
MICO_I2C_1,
MICO_I2C_MAX, /* Denotes the total number of I2C port aliases. Not a valid I2C alias */
MICO_I2C_NONE,
} mico_i2c_t;
typedef enum
{
MICO_IIS_MAX, /* Denotes the total number of IIS port aliases. Not a valid IIS alias */
MICO_IIS_NONE,
} mico_iis_t;
typedef enum
{
MICO_PWM_MAX, /* Denotes the total number of PWM port aliases. Not a valid PWM alias */
MICO_PWM_NONE,
} mico_pwm_t;
typedef enum
{
MICO_ADC_1,
MICO_ADC_2,
MICO_ADC_MAX, /* Denotes the total number of ADC port aliases. Not a valid ADC alias */
MICO_ADC_NONE,
} mico_adc_t;
typedef enum
{
MICO_UART_1,
MICO_UART_2,
MICO_UART_MAX, /* Denotes the total number of UART port aliases. Not a valid UART alias */
MICO_UART_NONE,
} mico_uart_t;
typedef hal_flash_t mico_flash_t;
typedef enum
{
MICO_PARTITION_FILESYS,
MICO_PARTITION_USER_MAX
} mico_user_partition_t;
#ifdef BOOTLOADER
#define STDIO_UART (MICO_UART_2)
#define STDIO_UART_BAUDRATE (921600)
#else
#define STDIO_UART (MICO_UART_1)
#define STDIO_UART_BAUDRATE (115200)
#endif
#define UART_FOR_APP (MICO_UART_2)
#define MFG_TEST (MICO_UART_2)
#define CLI_UART (MICO_UART_1)
/* Components connected to external I/Os*/
#define USE_MICO_SPI_FLASH
#define SFLASH_SUPPORT_MACRONIX_PARTS
//#define SFLASH_SUPPORT_SST_PARTS
//#define SFLASH_SUPPORT_WINBOND_PARTS
//#define USE_QUAD_SPI_FLASH
//#define USE_QUAD_SPI_DMA
#define BOOT_SEL (MICO_GPIO_36)
#define MFG_SEL (MICO_GPIO_37)
#define EasyLink_BUTTON (MICO_GPIO_9)
#define MICO_SYS_LED (MICO_GPIO_33)
#define MICO_RF_LED (MICO_GPIO_31)
/* Arduino extention connector */
#define Arduino_RXD (MICO_GPIO_29)
#define Arduino_TXD (MICO_GPIO_30)
#define Arduino_D2 (MICO_GPIO_NONE)
#define Arduino_D3 (MICO_GPIO_NONE)
#define Arduino_D4 (MICO_GPIO_19)
#define Arduino_D5 (MICO_GPIO_16)
#define Arduino_D6 (MICO_GPIO_14)
#define Arduino_D7 (MICO_GPIO_NONE)
#define Arduino_D8 (MICO_GPIO_2)
#define Arduino_D9 (MICO_GPIO_27)
#define Arduino_CS (MICO_GPIO_5)
#define Arduino_SI (MICO_GPIO_4)
#define Arduino_SO (MICO_GPIO_7)
#define Arduino_SCK (MICO_GPIO_6)
#define Arduino_SDA (MICO_GPIO_18)
#define Arduino_SCL (MICO_GPIO_17)
#define Arduino_A0 (MICO_ADC_NONE)
#define Arduino_A1 (MICO_ADC_NONE)
#define Arduino_A2 (MICO_ADC_1)
#define Arduino_A3 (MICO_ADC_2)
#define Arduino_A4 (MICO_ADC_NONE)
#define Arduino_A5 (MICO_ADC_NONE)
#define Arduino_I2C (MICO_I2C_1)
#define Arduino_SPI (MICO_SPI_1)
#define Arduino_UART (MICO_UART_2)
#ifdef USE_MiCOKit_EXT
#define MICO_I2C_CP (Arduino_I2C)
#include "micokit_ext_def.h"
#else
#define MICO_I2C_CP (MICO_I2C_NONE)
#endif //USE_MiCOKit_EXT

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Living_SDK/board/mk3165/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#define RHINO_CONFIG_MM_DEBUG 0
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#define RHINO_CONFIG_MM_LEAKCHECK 0
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
//#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
//#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 100
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#endif /* CONFIG_H */

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MEMORY
{
BL_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
APP_FLASH (rx) : ORIGIN = 0x0800C000, LENGTH = 900K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
ERAM (rwx) : ORIGIN = 0, LENGTH = 0
}

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Living_SDK/board/mk3165/mico_spi.c Normal file
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#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "mico_platform.h"
extern platform_spi_driver_t platform_spi_drivers[];
extern const platform_gpio_t platform_gpio_pins[];
extern const platform_spi_t platform_spi_peripherals[];
OSStatus MicoSpiInitialize( const platforom_spi_device_t* spi )
{
platform_spi_config_t config;
OSStatus err = kNoErr;
if ( spi->port >= MICO_SPI_NONE )
return kUnsupportedErr;
#ifdef MICO_WIFI_SHARE_SPI_BUS
if( platform_spi_peripherals[spi->port].port == wifi_spi.port )
{
return platform_wlan_spi_init( &platform_gpio_pins[spi->chip_select] );
}
#endif
if( platform_spi_drivers[spi->port].spi_mutex == NULL)
mico_rtos_init_mutex( &platform_spi_drivers[spi->port].spi_mutex );
config.chip_select = spi->chip_select == MICO_GPIO_NONE ? NULL : &platform_gpio_pins[spi->chip_select];
config.speed = spi->speed;
config.mode = spi->mode;
config.bits = spi->bits;
mico_rtos_lock_mutex( &platform_spi_drivers[spi->port].spi_mutex );
err = platform_spi_init( &platform_spi_drivers[spi->port], &platform_spi_peripherals[spi->port], &config );
mico_rtos_unlock_mutex( &platform_spi_drivers[spi->port].spi_mutex );
return err;
}
OSStatus MicoSpiFinalize( const platforom_spi_device_t* spi )
{
OSStatus err = kNoErr;
if ( spi->port >= MICO_SPI_NONE )
return kUnsupportedErr;
#ifdef MICO_WIFI_SHARE_SPI_BUS
if( platform_spi_peripherals[spi->port].port == wifi_spi.port )
{
return kUnsupportedErr;
//return platform_wlan_spi_deinit( &platform_gpio_pins[spi->chip_select] );
}
#endif
if( platform_spi_drivers[spi->port].spi_mutex == NULL)
mico_rtos_init_mutex( &platform_spi_drivers[spi->port].spi_mutex );
mico_rtos_lock_mutex( &platform_spi_drivers[spi->port].spi_mutex );
err = platform_spi_deinit( &platform_spi_drivers[spi->port] );
mico_rtos_unlock_mutex( &platform_spi_drivers[spi->port].spi_mutex );
return err;
}
OSStatus MicoSpiTransfer( const platforom_spi_device_t* spi, const platform_spi_message_segment_t* segments, uint16_t number_of_segments )
{
platform_spi_config_t config;
OSStatus err = kNoErr;
if ( spi->port >= MICO_SPI_NONE )
return kUnsupportedErr;
#ifdef MICO_WIFI_SHARE_SPI_BUS
if( platform_spi_peripherals[spi->port].port == wifi_spi.port )
{
return platform_wlan_spi_transfer( &platform_gpio_pins[spi->chip_select], segments, number_of_segments );
}
#endif
if( platform_spi_drivers[spi->port].spi_mutex == NULL)
mico_rtos_init_mutex( &platform_spi_drivers[spi->port].spi_mutex );
config.chip_select = spi->chip_select == MICO_GPIO_NONE ? NULL : &platform_gpio_pins[spi->chip_select];
config.speed = spi->speed;
config.mode = spi->mode;
config.bits = spi->bits;
mico_rtos_lock_mutex( &platform_spi_drivers[spi->port].spi_mutex );
err = platform_spi_init( &platform_spi_drivers[spi->port], &platform_spi_peripherals[spi->port], &config );
err = platform_spi_transfer( &platform_spi_drivers[spi->port], &config, segments, number_of_segments );
mico_rtos_unlock_mutex( &platform_spi_drivers[spi->port].spi_mutex );
return err;
}

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NAME := board_mk3165
JTAG := jlink_swd
$(NAME)_TYPE := kernel
MODULE := 3165
HOST_ARCH := Cortex-M4
HOST_MCU_FAMILY := stm32f4xx
HOST_MCU_VARIANT := STM32F411
SUPPORT_BINS := no
BUS := SDIO
$(NAME)_SOURCES := board.c mico_spi.c
$(NAME)_PREBUILT_LIBRARY := MiCO.$(MODULE).$(TOOLCHAIN_NAME).a
GLOBAL_INCLUDES += ./
GLOBAL_DEFINES += HSE_VALUE=26000000
GLOBAL_DEFINES += STDIO_UART=0
GLOBAL_DEFINES += RHINO_CONFIG_TICK_TASK=0 RHINO_CONFIG_WORKQUEUE=0
GLOBAL_DEFINES += MBEDTLS_AES_ROM_TABLES
GLOBAL_DEFINES += BOARD_MK3165
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_MK3165
CONFIG_SYSINFO_DEVICE_NAME := MK3165
GLOBAL_CFLAGS += -DSYSINFO_OS_VERSION=\"$(CONFIG_SYSINFO_OS_VERSION)\"
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
GLOBAL_LDFLAGS += -L $(SOURCE_ROOT)/board/mk3165
# Global defines
# HSE_VALUE = STM32 crystal frequency = 26MHz (needed to make UART work correctly)
GLOBAL_DEFINES += $$(if $$(NO_CRLF_STDIO_REPLACEMENT),,CRLF_STDIO_REPLACEMENT)
GLOBAL_CFLAGS += -DSTM32F411 -mcpu=cortex-m4 -mthumb -mfloat-abi=soft
WIFI_FIRMWARE_SECTOR_START := 2 #0x2000
FILESYSTEM_IMAGE_SECTOR_START := 256 #0x100000
# Extra build target in mico_standard_targets.mk, include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
EXTRA_TARGET_MAKEFILES += $(MAKEFILES_PATH)/aos_standard_targets.mk
#EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk
GLOBAL_DEFINES += LOCAL_PORT_ENHANCED_RAND