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https://github.com/Ai-Thinker-Open/Ai-Thinker-Open_RTL8710BX_ALIOS_SDK.git
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rel_1.6.0 init
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shengdong.dsd
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309
Living_SDK/board/lpcxpresso54102/clock_config.c
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309
Living_SDK/board/lpcxpresso54102/clock_config.c
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/*
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* Copyright 2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* How to set up clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Setup voltage for the fastest of the clock outputs
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*
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* 3. Set up wait states of the flash.
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*
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* 4. Set up all dividers.
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*
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* 5. Set up all selectors to provide selected clocks.
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*/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v3.0
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processor: LPC54102J512
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package_id: LPC54102J512BD64
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mcu_data: ksdk2_0
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processor_version: 0.0.0
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board: LPCXpresso54102
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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#include "fsl_power.h"
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#include "fsl_clock.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockPLL96M();
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockIRC12M **********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockIRC12M
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outputs:
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- {id: ASYNCAPB_clock.outFreq, value: 12 MHz}
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- {id: System_clock.outFreq, value: 12 MHz}
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- {id: TRACE_clock.outFreq, value: 12 MHz}
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sources:
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- {id: SYSCON.clk_in.outFreq, value: 4 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockIRC12M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockIRC12M configuration
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******************************************************************************/
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void BOARD_BootClockIRC12M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up IRC */
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POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC); /*!< Ensure IRC OSC is on */
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POWER_DisablePD(kPDRUNCFG_PD_IRC); /*!< Ensure IRC is on */
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CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
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/*!< PLL is in power_down mode */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to IRC12M */
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/*< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKIRC12M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL48M **********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL48M
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outputs:
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- {id: ASYNCAPB_clock.outFreq, value: 48 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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- {id: TRACE_clock.outFreq, value: 48 MHz}
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settings:
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- {id: PLL_Mode, value: Fractional}
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- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
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- {id: SYSCON.M_MULT.scale, value: '49152', locked: true}
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- {id: SYSCON.N_DIV.scale, value: '3', locked: true}
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- {id: SYSCON.PDEC.scale, value: '2', locked: true}
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- {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.DIRECTO}
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- {id: 'SYSCON::SYSPLLSSCTRL0[MDEC].bitField', value: '3'}
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- {id: SYSCON_SYSPLLCTRL_BYPASSCCODIV2_CFG, value: Enabled}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL48M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL48M configuration
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******************************************************************************/
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void BOARD_BootClockPLL48M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up IRC */
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POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC); /*!< Ensure IRC OSC is on */
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POWER_DisablePD(kPDRUNCFG_PD_IRC); /*!< Ensure IRC is on */
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CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
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/*!< Set up PLL */
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POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL); /*!< Ensure PLL is on */
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const pll_setup_t pllSetup = {
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.syspllctrl = SYSCON_SYSPLLCTRL_UPLIMOFF_MASK | SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK,
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.syspllndec = SYSCON_SYSPLLNDEC_NDEC(1U),
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.syspllpdec = SYSCON_SYSPLLPDEC_PDEC(98U),
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.syspllssctrl = {0x0U,(SYSCON_SYSPLLSSCTRL1_MD(49152U) | (uint32_t)(kSS_MF_512) | (uint32_t)(kSS_MR_K0) | (uint32_t)(kSS_MC_NOC))},
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.pllRate = 48000000U,
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.flags = PLL_SETUPFLAG_POWERUP
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};
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CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */
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/* PLL in Fractional/Spread spectrum mode */
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/* SYSTICK is used for waiting for PLL stabilization */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kSYS_PLL_OUT_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL_OUT */
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/*< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL48M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL96M **********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL96M
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called_from_default_init: true
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outputs:
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- {id: ASYNCAPB_clock.outFreq, value: 96 MHz}
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- {id: System_clock.outFreq, value: 96 MHz}
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- {id: TRACE_clock.outFreq, value: 96 MHz}
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settings:
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- {id: PLL_Mode, value: Fractional}
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- {id: SYSCON.DIRECTO.sel, value: SYSCON.PLL}
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- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
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- {id: SYSCON.M_MULT.scale, value: '49152', locked: true}
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- {id: SYSCON.N_DIV.scale, value: '3', locked: true}
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- {id: SYSCON.PDEC.scale, value: '2', locked: true}
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- {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.DIRECTO}
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- {id: 'SYSCON::SYSPLLSSCTRL0[MDEC].bitField', value: '3'}
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- {id: SYSCON_SYSPLLCTRL_BYPASSCCODIV2_CFG, value: Enabled}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL96M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL96M configuration
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******************************************************************************/
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void BOARD_BootClockPLL96M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up IRC */
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POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC); /*!< Ensure IRC OSC is on */
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POWER_DisablePD(kPDRUNCFG_PD_IRC); /*!< Ensure IRC is on */
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CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
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/*!< Set up PLL */
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POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL); /*!< Ensure PLL is on */
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const pll_setup_t pllSetup = {
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.syspllctrl = SYSCON_SYSPLLCTRL_UPLIMOFF_MASK | SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK | SYSCON_SYSPLLCTRL_DIRECTO_MASK,
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.syspllndec = SYSCON_SYSPLLNDEC_NDEC(1U),
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.syspllpdec = SYSCON_SYSPLLPDEC_PDEC(98U),
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.syspllssctrl = {0x0U,(SYSCON_SYSPLLSSCTRL1_MD(49152U) | (uint32_t)(kSS_MF_512) | (uint32_t)(kSS_MR_K0) | (uint32_t)(kSS_MC_NOC))},
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.pllRate = 96000000U,
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.flags = PLL_SETUPFLAG_POWERUP
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};
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CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */
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/* PLL in Fractional/Spread spectrum mode */
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/* SYSTICK is used for waiting for PLL stabilization */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kSYS_PLL_OUT_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL_OUT */
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/*< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL96M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL100M *********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL100M
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outputs:
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- {id: ASYNCAPB_clock.outFreq, value: 100 MHz}
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- {id: System_clock.outFreq, value: 100 MHz}
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- {id: TRACE_clock.outFreq, value: 100 MHz}
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settings:
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- {id: PLL_Mode, value: Fractional}
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- {id: SYSCON.DIRECTO.sel, value: SYSCON.PLL}
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- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
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- {id: SYSCON.M_MULT.scale, value: '102400', locked: true}
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- {id: SYSCON.N_DIV.scale, value: '6', locked: true}
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- {id: SYSCON.PDEC.scale, value: '2', locked: true}
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- {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.DIRECTO}
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- {id: 'SYSCON::SYSPLLSSCTRL0[MDEC].bitField', value: '32597'}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL100M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL100M configuration
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******************************************************************************/
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void BOARD_BootClockPLL100M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up IRC */
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POWER_DisablePD(kPDRUNCFG_PD_IRC_OSC); /*!< Ensure IRC OSC is on */
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POWER_DisablePD(kPDRUNCFG_PD_IRC); /*!< Ensure IRC is on */
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CLOCK_AttachClk(kIRC12M_to_MAIN_CLK); /*!< Switch to IRC 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
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/*!< Set up PLL */
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POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL); /*!< Ensure PLL is on */
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const pll_setup_t pllSetup = {
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.syspllctrl = SYSCON_SYSPLLCTRL_UPLIMOFF_MASK | SYSCON_SYSPLLCTRL_DIRECTO_MASK,
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.syspllndec = SYSCON_SYSPLLNDEC_NDEC(11U),
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.syspllpdec = SYSCON_SYSPLLPDEC_PDEC(98U),
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.syspllssctrl = {0x0U,(SYSCON_SYSPLLSSCTRL1_MD(51200U) | (uint32_t)(kSS_MF_512) | (uint32_t)(kSS_MR_K0) | (uint32_t)(kSS_MC_NOC))},
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.pllRate = 100000000U,
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.flags = PLL_SETUPFLAG_POWERUP
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};
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CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */
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/* PLL in Fractional/Spread spectrum mode */
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/* SYSTICK is used for waiting for PLL stabilization */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kSYS_PLL_OUT_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL_OUT */
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/*< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
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}
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