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231
Living_SDK/board/frdmkl27z/clock_config.c
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231
Living_SDK/board/frdmkl27z/clock_config.c
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/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
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* and flash clock are in allowed range during clock mode switch.
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*
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* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
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*
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* 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
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*
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* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
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*/
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!ClocksProfile
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product: Clocks v1.0
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processor: MKL27Z64xxx4
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package_id: MKL27Z64VLH4
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mcu_data: ksdk2_0
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processor_version: 1.0.1
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board: FRDM-KL27Z
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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#include "fsl_smc.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!Configuration
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name: BOARD_BootClockRUN
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outputs:
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- {id: Bus_clock.outFreq, value: 24 MHz}
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- {id: Core_clock.outFreq, value: 48 MHz}
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- {id: Flash_clock.outFreq, value: 24 MHz}
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- {id: LPO_clock.outFreq, value: 1 kHz}
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- {id: MCGIRCLK.outFreq, value: 8 MHz}
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- {id: MCGPCLK.outFreq, value: 48 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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settings:
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- {id: MCGMode, value: HIRC}
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- {id: MCG.CLKS.sel, value: MCG.HIRC}
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- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
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- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
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- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
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- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
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- {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC12PF}
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- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
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- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
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- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
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- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
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- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
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- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
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- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
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- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
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sources:
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- {id: MCG.HIRC.outFreq, value: 48 MHz}
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- {id: OSC.OSC.outFreq, value: 32.768 kHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
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{
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.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
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.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
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.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
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.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
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.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
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.hircEnableInNotHircMode = true, /* HIRC source is enabled */
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};
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const sim_clock_config_t simConfig_BOARD_BootClockRUN =
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{
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.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
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.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
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};
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const osc_config_t oscConfig_BOARD_BootClockRUN =
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{
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.freq = 0U, /* Oscillator frequency: 0Hz */
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.capLoad = (kOSC_Cap4P | kOSC_Cap8P), /* Oscillator capacity load: 12pF */
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.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
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}
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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{
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/* Set the system clock dividers in SIM to safe value. */
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CLOCK_SetSimSafeDivs();
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/* Set MCG to HIRC mode. */
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CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
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/* Set the clock configuration in SIM module. */
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CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
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}
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/*******************************************************************************
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********************* Configuration BOARD_BootClockVLPR ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!Configuration
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name: BOARD_BootClockVLPR
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outputs:
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- {id: Bus_clock.outFreq, value: 1 MHz}
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- {id: Core_clock.outFreq, value: 2 MHz}
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- {id: Flash_clock.outFreq, value: 1 MHz}
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- {id: LPO_clock.outFreq, value: 1 kHz}
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- {id: MCGIRCLK.outFreq, value: 2 MHz}
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- {id: System_clock.outFreq, value: 2 MHz}
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settings:
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- {id: MCGMode, value: LIRC2M}
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- {id: powerMode, value: VLPR}
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- {id: MCG.LIRCDIV1.scale, value: '1', locked: true}
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- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
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- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
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- {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC12PF}
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- {id: RTCCLKOUTConfig, value: 'yes'}
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- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
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- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
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- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
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sources:
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- {id: MCG.LIRC.outFreq, value: 2 MHz}
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- {id: OSC.OSC.outFreq, value: 32.768 kHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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/*******************************************************************************
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* Variables for BOARD_BootClockVLPR configuration
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******************************************************************************/
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const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
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{
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.outSrc = kMCGLITE_ClkSrcLirc, /* MCGOUTCLK source is LIRC */
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.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
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.ircs = kMCGLITE_Lirc2M, /* Slow internal reference (LIRC) 2 MHz clock selected */
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.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
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.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
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.hircEnableInNotHircMode = false, /* HIRC source is not enabled */
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};
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const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
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{
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.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
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.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
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};
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const osc_config_t oscConfig_BOARD_BootClockVLPR =
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{
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.freq = 0U, /* Oscillator frequency: 0Hz */
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.capLoad = (kOSC_Cap4P | kOSC_Cap8P), /* Oscillator capacity load: 12pF */
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.workMode = kOSC_ModeExt, /* Use external clock */
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
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}
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};
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/*******************************************************************************
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* Code for BOARD_BootClockVLPR configuration
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******************************************************************************/
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void BOARD_BootClockVLPR(void)
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{
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/* Set the system clock dividers in SIM to safe value. */
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CLOCK_SetSimSafeDivs();
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/* Set MCG to LIRC2M mode. */
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CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
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/* Set the clock configuration in SIM module. */
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CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
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/* Set VLPR power mode. */
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SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
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#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
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SMC_SetPowerModeVlpr(SMC, false);
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#else
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SMC_SetPowerModeVlpr(SMC);
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#endif
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while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
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{
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}
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
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}
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