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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
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56
Living_SDK/board/frdmkl27z/board.c Normal file
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/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include "fsl_common.h"
#include "board.h"
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* Initialize debug console. */
void BOARD_InitDebugConsole(void)
{
/* SIM_SOPT2[27:26]:
* 00: Clock Disabled
* 01: IRC48M
* 10: OSCERCLK
* 11: MCGIRCCLK
*/
CLOCK_SetLpuart0Clock(1);
}

75
Living_SDK/board/frdmkl27z/board.h Normal file
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/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include "clock_config.h"
#include "fsl_gpio.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* The board name */
#define BOARD_NAME "FRDM-KL27Z"
/* The LPUART to use for debug messages. */
#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0
#define BOARD_DEBUG_UART_INSTANCE 0U
#define BOARD_DEBUG_UART_CLKSRC kCLOCK_McgIrc48MClk
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetPeriphClkFreq()
#define BOARD_UART_IRQ LPUART0_IRQn
#define BOARD_UART_IRQ_HANDLER LPUART0_IRQHandler
#ifndef BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE 115200
#endif /* BOARD_DEBUG_UART_BAUDRATE */
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* API
******************************************************************************/
void BOARD_InitDebugConsole(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _BOARD_H_ */

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Living_SDK/board/frdmkl27z/clock_config.c Normal file
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/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* How to setup clock using clock driver functions:
*
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
* and flash clock are in allowed range during clock mode switch.
*
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
*
* 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
*
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
*/
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!ClocksProfile
product: Clocks v1.0
processor: MKL27Z64xxx4
package_id: MKL27Z64VLH4
mcu_data: ksdk2_0
processor_version: 1.0.1
board: FRDM-KL27Z
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
#include "fsl_smc.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!Configuration
name: BOARD_BootClockRUN
outputs:
- {id: Bus_clock.outFreq, value: 24 MHz}
- {id: Core_clock.outFreq, value: 48 MHz}
- {id: Flash_clock.outFreq, value: 24 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: MCGIRCLK.outFreq, value: 8 MHz}
- {id: MCGPCLK.outFreq, value: 48 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
settings:
- {id: MCGMode, value: HIRC}
- {id: MCG.CLKS.sel, value: MCG.HIRC}
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
- {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC12PF}
- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
sources:
- {id: MCG.HIRC.outFreq, value: 48 MHz}
- {id: OSC.OSC.outFreq, value: 32.768 kHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
{
.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
.hircEnableInNotHircMode = true, /* HIRC source is enabled */
};
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
{
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
};
const osc_config_t oscConfig_BOARD_BootClockRUN =
{
.freq = 0U, /* Oscillator frequency: 0Hz */
.capLoad = (kOSC_Cap4P | kOSC_Cap8P), /* Oscillator capacity load: 12pF */
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
}
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Set MCG to HIRC mode. */
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Bus_clock.outFreq, value: 1 MHz}
- {id: Core_clock.outFreq, value: 2 MHz}
- {id: Flash_clock.outFreq, value: 1 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: MCGIRCLK.outFreq, value: 2 MHz}
- {id: System_clock.outFreq, value: 2 MHz}
settings:
- {id: MCGMode, value: LIRC2M}
- {id: powerMode, value: VLPR}
- {id: MCG.LIRCDIV1.scale, value: '1', locked: true}
- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
- {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC12PF}
- {id: RTCCLKOUTConfig, value: 'yes'}
- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
sources:
- {id: MCG.LIRC.outFreq, value: 2 MHz}
- {id: OSC.OSC.outFreq, value: 32.768 kHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
/*******************************************************************************
* Variables for BOARD_BootClockVLPR configuration
******************************************************************************/
const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
{
.outSrc = kMCGLITE_ClkSrcLirc, /* MCGOUTCLK source is LIRC */
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
.ircs = kMCGLITE_Lirc2M, /* Slow internal reference (LIRC) 2 MHz clock selected */
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
.hircEnableInNotHircMode = false, /* HIRC source is not enabled */
};
const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
{
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
};
const osc_config_t oscConfig_BOARD_BootClockVLPR =
{
.freq = 0U, /* Oscillator frequency: 0Hz */
.capLoad = (kOSC_Cap4P | kOSC_Cap8P), /* Oscillator capacity load: 12pF */
.workMode = kOSC_ModeExt, /* Use external clock */
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
}
};
/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
void BOARD_BootClockVLPR(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Set MCG to LIRC2M mode. */
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
SMC_SetPowerModeVlpr(SMC, false);
#else
SMC_SetPowerModeVlpr(SMC);
#endif
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
}

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/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*! @brief MCG lite set for BOARD_BootClockRUN configuration.
*/
extern const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN;
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
*/
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
/*! @brief OSC set for BOARD_BootClockRUN configuration.
*/
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockVLPR configuration
******************************************************************************/
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 2000000U /*!< Core clock frequency: 2000000Hz */
/*! @brief MCG lite set for BOARD_BootClockVLPR configuration.
*/
extern const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR;
/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
*/
extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
/*! @brief OSC set for BOARD_BootClockVLPR configuration.
*/
extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
/*******************************************************************************
* API for BOARD_BootClockVLPR configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockVLPR(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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Living_SDK/board/frdmkl27z/frdmkl27z.mk Normal file
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NAME := board_frdmkl27z
MODULE := 27
HOST_ARCH := Cortex-M0
HOST_MCU_FAMILY := mkl27z644
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_MKL27Z644
CONFIG_SYSINFO_DEVICE_NAME := MKL27Z644
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
GLOBAL_CFLAGS += -DSYSINFO_ARCH=\"$(HOST_ARCH)\"
GLOBAL_CFLAGS += -DSYSINFO_MCU=\"$(HOST_MCU_FAMILY)\"
GLOBAL_CFLAGS += -DCONFIG_NO_TCPIP
GLOBAL_CFLAGS += -DFRDM_KL27Z -DFREEDOM
GLOBAL_LDFLAGS +=
GLOBAL_INCLUDES += .
GLOBAL_INCLUDES += ../../platform/mcu/mkl27z644/
GLOBAL_INCLUDES += ../../platform/mcu/mkl27z644/CMSIS/Include
GLOBAL_INCLUDES += ../../platform/mcu/mkl27z644/drivers
$(NAME)_SOURCES :=
$(NAME)_SOURCES += ./board.c
$(NAME)_SOURCES += ./clock_config.c
$(NAME)_SOURCES += ./pin_mux.c
TEST_COMPONENTS += certificate
GLOBAL_CFLAGS += -DTEST_CONFIG_KV_ENABLED=0
GLOBAL_CFLAGS += -DTEST_CONFIG_YLOOP_ENABLED=0

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Living_SDK/board/frdmkl27z/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef K_CONFIG_H
#define K_CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 0
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 13
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 0
#endif
#define K_MM_STATISTIC 0
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 10
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 10
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 64
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 0
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 100
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 200
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 8u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 0
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 64
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 5
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 256
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
#endif /* K_CONFIG_H */

635
Living_SDK/board/frdmkl27z/pin_mux.c Normal file
View file

@ -0,0 +1,635 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v4.0
processor: MKL27Z64xxx4
package_id: MKL27Z64VLH4
mcu_data: ksdk2_0
processor_version: 3.0.0
board: FRDM-KL27Z
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitLEDs:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '29', peripheral: GPIOA, signal: 'GPIO, 13', pin_signal: PTA13/TPM1_CH1, direction: OUTPUT, slew_rate: slow, pull_select: down, pull_enable: disable}
- {pin_num: '41', peripheral: GPIOB, signal: 'GPIO, 18', pin_signal: PTB18/TPM2_CH0, direction: OUTPUT, slew_rate: slow, pull_select: down, pull_enable: disable}
- {pin_num: '42', peripheral: GPIOB, signal: 'GPIO, 19', pin_signal: PTB19/TPM2_CH1, direction: OUTPUT, slew_rate: slow, pull_select: down, pull_enable: disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitLEDs
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitLEDs(void)
{
/* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortA);
/* Port B Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortB);
const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Slow slew rate is configured */
kPORT_SlowSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as PTA13 */
kPORT_MuxAsGpio};
/* PORTA13 (pin 29) is configured as PTA13 */
PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Slow slew rate is configured */
kPORT_SlowSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as PTB18 */
kPORT_MuxAsGpio};
/* PORTB18 (pin 41) is configured as PTB18 */
PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Slow slew rate is configured */
kPORT_SlowSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as PTB19 */
kPORT_MuxAsGpio};
/* PORTB19 (pin 42) is configured as PTB19 */
PORT_SetPinConfig(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, &LED_GREEN);
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitButtons:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '26', peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: PTA4/I2C1_SDA/TPM0_CH1/NMI_b, direction: INPUT, slew_rate: fast, pull_select: up, pull_enable: enable,
passive_filter: disable}
- {pin_num: '44', peripheral: GPIOC, signal: 'GPIO, 1', pin_signal: ADC0_SE15/PTC1/LLWU_P6/RTC_CLKIN/I2C1_SCL/TPM0_CH0, direction: INPUT, slew_rate: fast, pull_select: up,
pull_enable: enable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitButtons
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitButtons(void)
{
/* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortA);
/* Port C Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortC);
const port_pin_config_t SW1 = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as PTA4 */
kPORT_MuxAsGpio};
/* PORTA4 (pin 26) is configured as PTA4 */
PORT_SetPinConfig(BOARD_SW1_PORT, BOARD_SW1_PIN, &SW1);
const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as PTC1 */
kPORT_MuxAsGpio};
/* PORTC1 (pin 44) is configured as PTC1 */
PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitTSI:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '17', peripheral: GPIOE, signal: 'GPIO, 29', pin_signal: CMP0_IN5/ADC0_SE4b/PTE29/TPM0_CH2/TPM_CLKIN0, direction: INPUT, slew_rate: slow, pull_select: up,
pull_enable: disable}
- {pin_num: '18', peripheral: GPIOE, signal: 'GPIO, 30', pin_signal: ADC0_SE23/CMP0_IN4/PTE30/TPM0_CH3/TPM_CLKIN1/LPUART1_TX/LPTMR0_ALT1, direction: INPUT, slew_rate: slow,
pull_select: up, pull_enable: disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitTSI
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitTSI(void)
{
/* Port E Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortE);
/* PORTE29 (pin 17) is configured as PTE29 */
PORT_SetPinMux(BOARD_TOUCH_A_PORT, BOARD_TOUCH_A_PIN, kPORT_MuxAsGpio);
PORTE->PCR[29] = ((PORTE->PCR[29] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output. */
| PORT_PCR_SRE(kPORT_SlowSlewRate));
/* PORTE30 (pin 18) is configured as PTE30 */
PORT_SetPinMux(BOARD_TOUCH_B_PORT, BOARD_TOUCH_B_PIN, kPORT_MuxAsGpio);
PORTE->PCR[30] = ((PORTE->PCR[30] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output. */
| PORT_PCR_SRE(kPORT_SlowSlewRate));
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitUSB:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '5', peripheral: USB0, signal: DP, pin_signal: USB0_DP}
- {pin_num: '6', peripheral: USB0, signal: DM, pin_signal: USB0_DM}
- {pin_num: '27', peripheral: USB0, signal: CLKIN, pin_signal: PTA5/USB_CLKIN/TPM0_CH2, slew_rate: fast, pull_select: up, pull_enable: disable}
- {pin_num: '7', peripheral: USB0, signal: VDD, pin_signal: USB_VDD}
- {pin_num: '43', peripheral: USB0, signal: SOF_OUT, pin_signal: ADC0_SE14/PTC0/EXTRG_IN/USB_SOF_OUT/CMP0_OUT, slew_rate: fast, pull_select: up, pull_enable: disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitUSB
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitUSB(void)
{
/* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortA);
/* Port C Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortC);
/* PORTA5 (pin 27) is configured as USB_CLKIN */
PORT_SetPinMux(BOARD_TPM0_CH2_PORT, BOARD_TPM0_CH2_PIN, kPORT_MuxAlt2);
PORTA->PCR[5] = ((PORTA->PCR[5] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output. */
| PORT_PCR_SRE(kPORT_FastSlewRate));
/* PORTC0 (pin 43) is configured as USB_SOF_OUT */
PORT_SetPinMux(BOARD_USB_SOF_OUT_PORT, BOARD_USB_SOF_OUT_PIN, kPORT_MuxAlt4);
PORTC->PCR[0] = ((PORTC->PCR[0] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output. */
| PORT_PCR_SRE(kPORT_FastSlewRate));
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitACCEL_I2C:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '46', peripheral: GPIOC, signal: 'GPIO, 3', pin_signal: PTC3/LLWU_P7/SPI1_SCK/LPUART1_RX/TPM0_CH2/CLKOUT, direction: INPUT, drive_strength: low, pull_select: up,
pull_enable: disable}
- {pin_num: '45', peripheral: GPIOC, signal: 'GPIO, 2', pin_signal: ADC0_SE11/PTC2/I2C1_SDA/TPM0_CH1, identifier: INT2_ACCEL, direction: INPUT, slew_rate: fast,
pull_select: up, pull_enable: disable}
- {pin_num: '63', peripheral: I2C1, signal: SDA, pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI1_MOSI/LPUART0_RX/I2C1_SDA/SPI1_MISO/FXIO0_D6, identifier: ACCEL_I2C1_SDA}
- {pin_num: '64', peripheral: I2C1, signal: SCL, pin_signal: PTD7/SPI1_MISO/LPUART0_TX/I2C1_SCL/SPI1_MOSI/FXIO0_D7, identifier: ACCEL_I2C1_SCL}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitACCEL_I2C
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitACCEL_I2C(void)
{
/* Port C Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortC);
/* Port D Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortD);
/* PORTC2 (pin 45) is configured as PTC2 */
PORT_SetPinMux(BOARD_INT2_ACCEL_PORT, BOARD_INT2_ACCEL_PIN, kPORT_MuxAsGpio);
PORTC->PCR[2] = ((PORTC->PCR[2] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output. */
| PORT_PCR_SRE(kPORT_FastSlewRate));
/* PORTC3 (pin 46) is configured as PTC3 */
PORT_SetPinMux(BOARD_INT1_ACCEL_PORT, BOARD_INT1_ACCEL_PIN, kPORT_MuxAsGpio);
PORTC->PCR[3] = ((PORTC->PCR[3] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Drive Strength Enable: Low drive strength is configured on the corresponding pin, if pin
* is configured as a digital output. */
| PORT_PCR_DSE(kPORT_LowDriveStrength));
/* PORTD6 (pin 63) is configured as I2C1_SDA */
PORT_SetPinMux(BOARD_ACCEL_I2C1_SDA_PORT, BOARD_ACCEL_I2C1_SDA_PIN, kPORT_MuxAlt4);
/* PORTD7 (pin 64) is configured as I2C1_SCL */
PORT_SetPinMux(BOARD_ACCEL_I2C1_SCL_PORT, BOARD_ACCEL_I2C1_SCL_PIN, kPORT_MuxAlt4);
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitMAGNET_I2C:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '64', peripheral: I2C1, signal: SCL, pin_signal: PTD7/SPI1_MISO/LPUART0_TX/I2C1_SCL/SPI1_MOSI/FXIO0_D7, identifier: MAG_I2C1_SCL, slew_rate: fast, drive_strength: low,
pull_select: up, pull_enable: enable}
- {pin_num: '63', peripheral: I2C1, signal: SDA, pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI1_MOSI/LPUART0_RX/I2C1_SDA/SPI1_MISO/FXIO0_D6, identifier: MAG_I2C1_SDA,
slew_rate: fast, drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: '45', peripheral: GPIOC, signal: 'GPIO, 2', pin_signal: ADC0_SE11/PTC2/I2C1_SDA/TPM0_CH1, identifier: INT1_MAG, direction: INPUT, slew_rate: fast, pull_select: up,
pull_enable: disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitMAGNET_I2C
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitMAGNET_I2C(void)
{
/* Port C Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortC);
/* Port D Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortD);
/* PORTC2 (pin 45) is configured as PTC2 */
PORT_SetPinMux(BOARD_INT1_MAG_PORT, BOARD_INT1_MAG_PIN, kPORT_MuxAsGpio);
PORTC->PCR[2] = ((PORTC->PCR[2] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output. */
| PORT_PCR_SRE(kPORT_FastSlewRate));
const port_pin_config_t MAG_I2C1_SDA = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as I2C1_SDA */
kPORT_MuxAlt4};
/* PORTD6 (pin 63) is configured as I2C1_SDA */
PORT_SetPinConfig(BOARD_MAG_I2C1_SDA_PORT, BOARD_MAG_I2C1_SDA_PIN, &MAG_I2C1_SDA);
const port_pin_config_t MAG_I2C1_SCL = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as I2C1_SCL */
kPORT_MuxAlt4};
/* PORTD7 (pin 64) is configured as I2C1_SCL */
PORT_SetPinConfig(BOARD_MAG_I2C1_SCL_PORT, BOARD_MAG_I2C1_SCL_PIN, &MAG_I2C1_SCL);
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UART:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '23', peripheral: LPUART0, signal: RX, pin_signal: PTA1/LPUART0_RX/TPM2_CH0, slew_rate: fast, pull_select: down, pull_enable: disable}
- {pin_num: '24', peripheral: LPUART0, signal: TX, pin_signal: PTA2/LPUART0_TX/TPM2_CH1, direction: OUTPUT, slew_rate: fast, pull_select: down, pull_enable: disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UART
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UART(void)
{
/* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortA);
const port_pin_config_t DEBUG_UART0_RX = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as LPUART0_RX */
kPORT_MuxAlt2};
/* PORTA1 (pin 23) is configured as LPUART0_RX */
PORT_SetPinConfig(BOARD_DEBUG_UART0_RX_PORT, BOARD_DEBUG_UART0_RX_PIN, &DEBUG_UART0_RX);
const port_pin_config_t DEBUG_UART0_TX = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as LPUART0_TX */
kPORT_MuxAlt2};
/* PORTA2 (pin 24) is configured as LPUART0_TX */
PORT_SetPinConfig(BOARD_DEBUG_UART0_TX_PORT, BOARD_DEBUG_UART0_TX_PIN, &DEBUG_UART0_TX);
SIM->SOPT5 = ((SIM->SOPT5 &
/* Mask bits to zero which are setting */
(~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
/* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
| SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
/* LPUART0 Receive Data Source Select: LPUART_RX pin. */
| SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitTHER:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '11', peripheral: GPIOE, signal: 'GPIO, 22', pin_signal: ADC0_DP3/ADC0_SE3/PTE22/TPM2_CH0/UART2_TX/FXIO0_D6, direction: INPUT, slew_rate: slow, pull_select: up,
pull_enable: disable}
- {pin_num: '12', peripheral: GPIOE, signal: 'GPIO, 23', pin_signal: ADC0_DM3/ADC0_SE7a/PTE23/TPM2_CH1/UART2_RX/FXIO0_D7, direction: INPUT, slew_rate: slow, pull_select: up,
pull_enable: disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitTHER
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitTHER(void)
{
/* Port E Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortE);
/* PORTE22 (pin 11) is configured as PTE22 */
PORT_SetPinMux(BOARD_THER_A_PORT, BOARD_THER_A_PIN, kPORT_MuxAsGpio);
PORTE->PCR[22] = ((PORTE->PCR[22] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output. */
| PORT_PCR_SRE(kPORT_SlowSlewRate));
/* PORTE23 (pin 12) is configured as PTE23 */
PORT_SetPinMux(BOARD_THER_B_PORT, BOARD_THER_B_PIN, kPORT_MuxAsGpio);
PORTE->PCR[23] = ((PORTE->PCR[23] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK)))
/* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set. */
| PORT_PCR_PS(kPORT_PullUp)
/* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
| PORT_PCR_PE(kPORT_PullDisable)
/* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output. */
| PORT_PCR_SRE(kPORT_SlowSlewRate));
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitOSC:
- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '32', peripheral: OSC0, signal: EXTAL0, pin_signal: EXTAL0/PTA18/LPUART1_RX/TPM_CLKIN0, slew_rate: no_init, pull_select: no_init, pull_enable: no_init}
- {pin_num: '33', peripheral: OSC0, signal: XTAL0, pin_signal: XTAL0/PTA19/LPUART1_TX/TPM_CLKIN1/LPTMR0_ALT1, slew_rate: no_init, pull_select: no_init, pull_enable: no_init}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitOSC
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitOSC(void)
{
/* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortA);
/* PORTA18 (pin 32) is configured as EXTAL0 */
PORT_SetPinMux(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, kPORT_PinDisabledOrAnalog);
/* PORTA19 (pin 33) is configured as XTAL0 */
PORT_SetPinMux(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, kPORT_PinDisabledOrAnalog);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/*! @name PORTA13 (number 29), J1[10]/D4-TPM1_CH1/D4-LED_BLUE
@{ */
#define BOARD_LED_BLUE_PERIPHERAL GPIOA /*!<@brief Device name: GPIOA */
#define BOARD_LED_BLUE_SIGNAL GPIO /*!<@brief GPIOA signal: GPIO */
#define BOARD_LED_BLUE_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
#define BOARD_LED_BLUE_GPIO_PIN 13U /*!<@brief PORTA pin index: 13 */
#define BOARD_LED_BLUE_PORT PORTA /*!<@brief PORT device name: PORTA */
#define BOARD_LED_BLUE_PIN 13U /*!<@brief PORTA pin index: 13 */
#define BOARD_LED_BLUE_CHANNEL 13 /*!<@brief GPIOA GPIO channel: 13 */
#define BOARD_LED_BLUE_PIN_NAME PTA13 /*!<@brief Pin name */
#define BOARD_LED_BLUE_LABEL "J1[10]/D4-TPM1_CH1/D4-LED_BLUE" /*!<@brief Label */
#define BOARD_LED_BLUE_NAME "LED_BLUE" /*!<@brief Identifier name */
#define BOARD_LED_BLUE_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
/* @} */
/*! @name PORTB18 (number 41), J2[11]/D11[1]/LED_RED
@{ */
#define BOARD_LED_RED_PERIPHERAL GPIOB /*!<@brief Device name: GPIOB */
#define BOARD_LED_RED_SIGNAL GPIO /*!<@brief GPIOB signal: GPIO */
#define BOARD_LED_RED_GPIO GPIOB /*!<@brief GPIO device name: GPIOB */
#define BOARD_LED_RED_GPIO_PIN 18U /*!<@brief PORTB pin index: 18 */
#define BOARD_LED_RED_PORT PORTB /*!<@brief PORT device name: PORTB */
#define BOARD_LED_RED_PIN 18U /*!<@brief PORTB pin index: 18 */
#define BOARD_LED_RED_CHANNEL 18 /*!<@brief GPIOB GPIO channel: 18 */
#define BOARD_LED_RED_PIN_NAME PTB18 /*!<@brief Pin name */
#define BOARD_LED_RED_LABEL "J2[11]/D11[1]/LED_RED" /*!<@brief Label */
#define BOARD_LED_RED_NAME "LED_RED" /*!<@brief Identifier name */
#define BOARD_LED_RED_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
/* @} */
/*! @name PORTB19 (number 42), J2[13]/D11[4]/LED_GREEN
@{ */
#define BOARD_LED_GREEN_PERIPHERAL GPIOB /*!<@brief Device name: GPIOB */
#define BOARD_LED_GREEN_SIGNAL GPIO /*!<@brief GPIOB signal: GPIO */
#define BOARD_LED_GREEN_GPIO GPIOB /*!<@brief GPIO device name: GPIOB */
#define BOARD_LED_GREEN_GPIO_PIN 19U /*!<@brief PORTB pin index: 19 */
#define BOARD_LED_GREEN_PORT PORTB /*!<@brief PORT device name: PORTB */
#define BOARD_LED_GREEN_PIN 19U /*!<@brief PORTB pin index: 19 */
#define BOARD_LED_GREEN_CHANNEL 19 /*!<@brief GPIOB GPIO channel: 19 */
#define BOARD_LED_GREEN_PIN_NAME PTB19 /*!<@brief Pin name */
#define BOARD_LED_GREEN_LABEL "J2[13]/D11[4]/LED_GREEN" /*!<@brief Label */
#define BOARD_LED_GREEN_NAME "LED_GREEN" /*!<@brief Identifier name */
#define BOARD_LED_GREEN_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitLEDs(void);
/*! @name PORTA4 (number 26), J2[5]/SW1
@{ */
#define BOARD_SW1_PERIPHERAL GPIOA /*!<@brief Device name: GPIOA */
#define BOARD_SW1_SIGNAL GPIO /*!<@brief GPIOA signal: GPIO */
#define BOARD_SW1_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
#define BOARD_SW1_GPIO_PIN 4U /*!<@brief PORTA pin index: 4 */
#define BOARD_SW1_PORT PORTA /*!<@brief PORT device name: PORTA */
#define BOARD_SW1_PIN 4U /*!<@brief PORTA pin index: 4 */
#define BOARD_SW1_CHANNEL 4 /*!<@brief GPIOA GPIO channel: 4 */
#define BOARD_SW1_PIN_NAME PTA4 /*!<@brief Pin name */
#define BOARD_SW1_LABEL "J2[5]/SW1" /*!<@brief Label */
#define BOARD_SW1_NAME "SW1" /*!<@brief Identifier name */
#define BOARD_SW1_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*! @name PORTC1 (number 44), J3[13]/SW3
@{ */
#define BOARD_SW3_PERIPHERAL GPIOC /*!<@brief Device name: GPIOC */
#define BOARD_SW3_SIGNAL GPIO /*!<@brief GPIOC signal: GPIO */
#define BOARD_SW3_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
#define BOARD_SW3_GPIO_PIN 1U /*!<@brief PORTC pin index: 1 */
#define BOARD_SW3_PORT PORTC /*!<@brief PORT device name: PORTC */
#define BOARD_SW3_PIN 1U /*!<@brief PORTC pin index: 1 */
#define BOARD_SW3_CHANNEL 1 /*!<@brief GPIOC GPIO channel: 1 */
#define BOARD_SW3_PIN_NAME PTC1 /*!<@brief Pin name */
#define BOARD_SW3_LABEL "J3[13]/SW3" /*!<@brief Label */
#define BOARD_SW3_NAME "SW3" /*!<@brief Identifier name */
#define BOARD_SW3_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitButtons(void);
/*! @name PORTE29 (number 17), TOUCH_A
@{ */
#define BOARD_TOUCH_A_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
#define BOARD_TOUCH_A_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
#define BOARD_TOUCH_A_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
#define BOARD_TOUCH_A_GPIO_PIN 29U /*!<@brief PORTE pin index: 29 */
#define BOARD_TOUCH_A_PORT PORTE /*!<@brief PORT device name: PORTE */
#define BOARD_TOUCH_A_PIN 29U /*!<@brief PORTE pin index: 29 */
#define BOARD_TOUCH_A_CHANNEL 29 /*!<@brief GPIOE GPIO channel: 29 */
#define BOARD_TOUCH_A_PIN_NAME PTE29 /*!<@brief Pin name */
#define BOARD_TOUCH_A_LABEL "TOUCH_A" /*!<@brief Label */
#define BOARD_TOUCH_A_NAME "TOUCH_A" /*!<@brief Identifier name */
#define BOARD_TOUCH_A_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*! @name PORTE30 (number 18), TOUCH_B
@{ */
#define BOARD_TOUCH_B_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
#define BOARD_TOUCH_B_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
#define BOARD_TOUCH_B_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
#define BOARD_TOUCH_B_GPIO_PIN 30U /*!<@brief PORTE pin index: 30 */
#define BOARD_TOUCH_B_PORT PORTE /*!<@brief PORT device name: PORTE */
#define BOARD_TOUCH_B_PIN 30U /*!<@brief PORTE pin index: 30 */
#define BOARD_TOUCH_B_CHANNEL 30 /*!<@brief GPIOE GPIO channel: 30 */
#define BOARD_TOUCH_B_PIN_NAME PTE30 /*!<@brief Pin name */
#define BOARD_TOUCH_B_LABEL "TOUCH_B" /*!<@brief Label */
#define BOARD_TOUCH_B_NAME "TOUCH_B" /*!<@brief Identifier name */
#define BOARD_TOUCH_B_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitTSI(void);
/*! @name USB0_DP (number 5), J10[3]
@{ */
#define BOARD_USB_DP_PERIPHERAL USB0 /*!<@brief Device name: USB0 */
#define BOARD_USB_DP_SIGNAL DP /*!<@brief USB0 signal: DP */
#define BOARD_USB_DP_PIN_NAME USB0_DP /*!<@brief Pin name */
#define BOARD_USB_DP_LABEL "J10[3]" /*!<@brief Label */
#define BOARD_USB_DP_NAME "USB_DP" /*!<@brief Identifier name */
/* @} */
/*! @name USB0_DM (number 6), J10[2]
@{ */
#define BOARD_USB_DM_PERIPHERAL USB0 /*!<@brief Device name: USB0 */
#define BOARD_USB_DM_SIGNAL DM /*!<@brief USB0 signal: DM */
#define BOARD_USB_DM_PIN_NAME USB0_DM /*!<@brief Pin name */
#define BOARD_USB_DM_LABEL "J10[2]" /*!<@brief Label */
#define BOARD_USB_DM_NAME "USB_DM" /*!<@brief Identifier name */
/* @} */
/*! @name PORTA5 (number 27), J2[4]/D9-TPM0_CH2
@{ */
#define BOARD_TPM0_CH2_PERIPHERAL USB0 /*!<@brief Device name: USB0 */
#define BOARD_TPM0_CH2_SIGNAL CLKIN /*!<@brief USB0 signal: CLKIN */
#define BOARD_TPM0_CH2_PORT PORTA /*!<@brief PORT device name: PORTA */
#define BOARD_TPM0_CH2_PIN 5U /*!<@brief PORTA pin index: 5 */
#define BOARD_TPM0_CH2_PIN_NAME USB_CLKIN /*!<@brief Pin name */
#define BOARD_TPM0_CH2_LABEL "J2[4]/D9-TPM0_CH2" /*!<@brief Label */
#define BOARD_TPM0_CH2_NAME "TPM0_CH2" /*!<@brief Identifier name */
/* @} */
/*! @name USB_VDD (number 7), P3V3_KL27Z
@{ */
#define BOARD_USB_VDD_PERIPHERAL USB0 /*!<@brief Device name: USB0 */
#define BOARD_USB_VDD_SIGNAL VDD /*!<@brief USB0 signal: VDD */
#define BOARD_USB_VDD_PIN_NAME USB_VDD /*!<@brief Pin name */
#define BOARD_USB_VDD_LABEL "P3V3_KL27Z" /*!<@brief Label */
#define BOARD_USB_VDD_NAME "USB_VDD" /*!<@brief Identifier name */
/* @} */
/*! @name PORTC0 (number 43), J4[4]/A1-ADC0_SE14
@{ */
#define BOARD_USB_SOF_OUT_PERIPHERAL USB0 /*!<@brief Device name: USB0 */
#define BOARD_USB_SOF_OUT_SIGNAL SOF_OUT /*!<@brief USB0 signal: SOF_OUT */
#define BOARD_USB_SOF_OUT_PORT PORTC /*!<@brief PORT device name: PORTC */
#define BOARD_USB_SOF_OUT_PIN 0U /*!<@brief PORTC pin index: 0 */
#define BOARD_USB_SOF_OUT_PIN_NAME USB_SOF_OUT /*!<@brief Pin name */
#define BOARD_USB_SOF_OUT_LABEL "J4[4]/A1-ADC0_SE14" /*!<@brief Label */
#define BOARD_USB_SOF_OUT_NAME "USB_SOF_OUT" /*!<@brief Identifier name */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitUSB(void);
/*! @name PORTC3 (number 46), J2[15]/U10[11]/J28[1]/INT1_ACCEL
@{ */
#define BOARD_INT1_ACCEL_PERIPHERAL GPIOC /*!<@brief Device name: GPIOC */
#define BOARD_INT1_ACCEL_SIGNAL GPIO /*!<@brief GPIOC signal: GPIO */
#define BOARD_INT1_ACCEL_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
#define BOARD_INT1_ACCEL_GPIO_PIN 3U /*!<@brief PORTC pin index: 3 */
#define BOARD_INT1_ACCEL_PORT PORTC /*!<@brief PORT device name: PORTC */
#define BOARD_INT1_ACCEL_PIN 3U /*!<@brief PORTC pin index: 3 */
#define BOARD_INT1_ACCEL_CHANNEL 3 /*!<@brief GPIOC GPIO channel: 3 */
#define BOARD_INT1_ACCEL_PIN_NAME PTC3 /*!<@brief Pin name */
#define BOARD_INT1_ACCEL_LABEL "J2[15]/U10[11]/J28[1]/INT1_ACCEL" /*!<@brief Label */
#define BOARD_INT1_ACCEL_NAME "INT1_ACCEL" /*!<@brief Identifier name */
#define BOARD_INT1_ACCEL_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*! @name PORTC2 (number 45), J3[15]/U10[9]/J27[1]/UART1_TX/INT2_ACCEL
@{ */
#define BOARD_INT2_ACCEL_PERIPHERAL GPIOC /*!<@brief Device name: GPIOC */
#define BOARD_INT2_ACCEL_SIGNAL GPIO /*!<@brief GPIOC signal: GPIO */
#define BOARD_INT2_ACCEL_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
#define BOARD_INT2_ACCEL_GPIO_PIN 2U /*!<@brief PORTC pin index: 2 */
#define BOARD_INT2_ACCEL_PORT PORTC /*!<@brief PORT device name: PORTC */
#define BOARD_INT2_ACCEL_PIN 2U /*!<@brief PORTC pin index: 2 */
#define BOARD_INT2_ACCEL_CHANNEL 2 /*!<@brief GPIOC GPIO channel: 2 */
#define BOARD_INT2_ACCEL_PIN_NAME PTC2 /*!<@brief Pin name */
#define BOARD_INT2_ACCEL_LABEL "J3[15]/U10[9]/J27[1]/UART1_TX/INT2_ACCEL" /*!<@brief Label */
#define BOARD_INT2_ACCEL_NAME "INT2_ACCEL" /*!<@brief Identifier name */
#define BOARD_INT2_ACCEL_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*! @name PORTD6 (number 63), J2[18]/J24[1]/D14-I2C1_SDA
@{ */
#define BOARD_ACCEL_I2C1_SDA_PERIPHERAL I2C1 /*!<@brief Device name: I2C1 */
#define BOARD_ACCEL_I2C1_SDA_SIGNAL SDA /*!<@brief I2C1 signal: SDA */
#define BOARD_ACCEL_I2C1_SDA_PORT PORTD /*!<@brief PORT device name: PORTD */
#define BOARD_ACCEL_I2C1_SDA_PIN 6U /*!<@brief PORTD pin index: 6 */
#define BOARD_ACCEL_I2C1_SDA_PIN_NAME I2C1_SDA /*!<@brief Pin name */
#define BOARD_ACCEL_I2C1_SDA_LABEL "J2[18]/J24[1]/D14-I2C1_SDA" /*!<@brief Label */
#define BOARD_ACCEL_I2C1_SDA_NAME "ACCEL_I2C1_SDA" /*!<@brief Identifier name */
/* @} */
/*! @name PORTD7 (number 64), J2[20]/J23[1]/D15-I2C1_SCL
@{ */
#define BOARD_ACCEL_I2C1_SCL_PERIPHERAL I2C1 /*!<@brief Device name: I2C1 */
#define BOARD_ACCEL_I2C1_SCL_SIGNAL SCL /*!<@brief I2C1 signal: SCL */
#define BOARD_ACCEL_I2C1_SCL_PORT PORTD /*!<@brief PORT device name: PORTD */
#define BOARD_ACCEL_I2C1_SCL_PIN 7U /*!<@brief PORTD pin index: 7 */
#define BOARD_ACCEL_I2C1_SCL_PIN_NAME I2C1_SCL /*!<@brief Pin name */
#define BOARD_ACCEL_I2C1_SCL_LABEL "J2[20]/J23[1]/D15-I2C1_SCL" /*!<@brief Label */
#define BOARD_ACCEL_I2C1_SCL_NAME "ACCEL_I2C1_SCL" /*!<@brief Identifier name */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitACCEL_I2C(void);
/*! @name PORTD7 (number 64), J2[20]/J23[1]/D15-I2C1_SCL
@{ */
#define BOARD_MAG_I2C1_SCL_PERIPHERAL I2C1 /*!<@brief Device name: I2C1 */
#define BOARD_MAG_I2C1_SCL_SIGNAL SCL /*!<@brief I2C1 signal: SCL */
#define BOARD_MAG_I2C1_SCL_PORT PORTD /*!<@brief PORT device name: PORTD */
#define BOARD_MAG_I2C1_SCL_PIN 7U /*!<@brief PORTD pin index: 7 */
#define BOARD_MAG_I2C1_SCL_PIN_NAME I2C1_SCL /*!<@brief Pin name */
#define BOARD_MAG_I2C1_SCL_LABEL "J2[20]/J23[1]/D15-I2C1_SCL" /*!<@brief Label */
#define BOARD_MAG_I2C1_SCL_NAME "MAG_I2C1_SCL" /*!<@brief Identifier name */
/* @} */
/*! @name PORTD6 (number 63), J2[18]/J24[1]/D14-I2C1_SDA
@{ */
#define BOARD_MAG_I2C1_SDA_PERIPHERAL I2C1 /*!<@brief Device name: I2C1 */
#define BOARD_MAG_I2C1_SDA_SIGNAL SDA /*!<@brief I2C1 signal: SDA */
#define BOARD_MAG_I2C1_SDA_PORT PORTD /*!<@brief PORT device name: PORTD */
#define BOARD_MAG_I2C1_SDA_PIN 6U /*!<@brief PORTD pin index: 6 */
#define BOARD_MAG_I2C1_SDA_PIN_NAME I2C1_SDA /*!<@brief Pin name */
#define BOARD_MAG_I2C1_SDA_LABEL "J2[18]/J24[1]/D14-I2C1_SDA" /*!<@brief Label */
#define BOARD_MAG_I2C1_SDA_NAME "MAG_I2C1_SDA" /*!<@brief Identifier name */
/* @} */
/*! @name PORTC2 (number 45), J3[15]/U10[9]/J27[1]/UART1_TX/INT2_ACCEL
@{ */
#define BOARD_INT1_MAG_PERIPHERAL GPIOC /*!<@brief Device name: GPIOC */
#define BOARD_INT1_MAG_SIGNAL GPIO /*!<@brief GPIOC signal: GPIO */
#define BOARD_INT1_MAG_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
#define BOARD_INT1_MAG_GPIO_PIN 2U /*!<@brief PORTC pin index: 2 */
#define BOARD_INT1_MAG_PORT PORTC /*!<@brief PORT device name: PORTC */
#define BOARD_INT1_MAG_PIN 2U /*!<@brief PORTC pin index: 2 */
#define BOARD_INT1_MAG_CHANNEL 2 /*!<@brief GPIOC GPIO channel: 2 */
#define BOARD_INT1_MAG_PIN_NAME PTC2 /*!<@brief Pin name */
#define BOARD_INT1_MAG_LABEL "J3[15]/U10[9]/J27[1]/UART1_TX/INT2_ACCEL" /*!<@brief Label */
#define BOARD_INT1_MAG_NAME "INT1_MAG" /*!<@brief Identifier name */
#define BOARD_INT1_MAG_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitMAGNET_I2C(void);
#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */
#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */
/*! @name PORTA1 (number 23), J1[2]/J25[1]/D0-UART0_RX
@{ */
#define BOARD_DEBUG_UART0_RX_PERIPHERAL LPUART0 /*!<@brief Device name: LPUART0 */
#define BOARD_DEBUG_UART0_RX_SIGNAL RX /*!<@brief LPUART0 signal: RX */
#define BOARD_DEBUG_UART0_RX_PORT PORTA /*!<@brief PORT device name: PORTA */
#define BOARD_DEBUG_UART0_RX_PIN 1U /*!<@brief PORTA pin index: 1 */
#define BOARD_DEBUG_UART0_RX_PIN_NAME LPUART0_RX /*!<@brief Pin name */
#define BOARD_DEBUG_UART0_RX_LABEL "J1[2]/J25[1]/D0-UART0_RX" /*!<@brief Label */
#define BOARD_DEBUG_UART0_RX_NAME "DEBUG_UART0_RX" /*!<@brief Identifier name */
/* @} */
/*! @name PORTA2 (number 24), J1[4]/J26[1]/D1-UART0_TX
@{ */
#define BOARD_DEBUG_UART0_TX_PERIPHERAL LPUART0 /*!<@brief Device name: LPUART0 */
#define BOARD_DEBUG_UART0_TX_SIGNAL TX /*!<@brief LPUART0 signal: TX */
#define BOARD_DEBUG_UART0_TX_PORT PORTA /*!<@brief PORT device name: PORTA */
#define BOARD_DEBUG_UART0_TX_PIN 2U /*!<@brief PORTA pin index: 2 */
#define BOARD_DEBUG_UART0_TX_PIN_NAME LPUART0_TX /*!<@brief Pin name */
#define BOARD_DEBUG_UART0_TX_LABEL "J1[4]/J26[1]/D1-UART0_TX" /*!<@brief Label */
#define BOARD_DEBUG_UART0_TX_NAME "DEBUG_UART0_TX" /*!<@brief Identifier name */
#define BOARD_DEBUG_UART0_TX_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UART(void);
/*! @name PORTE22 (number 11), THER_A
@{ */
#define BOARD_THER_A_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
#define BOARD_THER_A_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
#define BOARD_THER_A_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
#define BOARD_THER_A_GPIO_PIN 22U /*!<@brief PORTE pin index: 22 */
#define BOARD_THER_A_PORT PORTE /*!<@brief PORT device name: PORTE */
#define BOARD_THER_A_PIN 22U /*!<@brief PORTE pin index: 22 */
#define BOARD_THER_A_CHANNEL 22 /*!<@brief GPIOE GPIO channel: 22 */
#define BOARD_THER_A_PIN_NAME PTE22 /*!<@brief Pin name */
#define BOARD_THER_A_LABEL "THER_A" /*!<@brief Label */
#define BOARD_THER_A_NAME "THER_A" /*!<@brief Identifier name */
#define BOARD_THER_A_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*! @name PORTE23 (number 12), THER_B
@{ */
#define BOARD_THER_B_PERIPHERAL GPIOE /*!<@brief Device name: GPIOE */
#define BOARD_THER_B_SIGNAL GPIO /*!<@brief GPIOE signal: GPIO */
#define BOARD_THER_B_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
#define BOARD_THER_B_GPIO_PIN 23U /*!<@brief PORTE pin index: 23 */
#define BOARD_THER_B_PORT PORTE /*!<@brief PORT device name: PORTE */
#define BOARD_THER_B_PIN 23U /*!<@brief PORTE pin index: 23 */
#define BOARD_THER_B_CHANNEL 23 /*!<@brief GPIOE GPIO channel: 23 */
#define BOARD_THER_B_PIN_NAME PTE23 /*!<@brief Pin name */
#define BOARD_THER_B_LABEL "THER_B" /*!<@brief Label */
#define BOARD_THER_B_NAME "THER_B" /*!<@brief Identifier name */
#define BOARD_THER_B_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitTHER(void);
/*! @name PORTA18 (number 32), EXTAL_32KHZ
@{ */
#define BOARD_EXTAL0_PERIPHERAL OSC0 /*!<@brief Device name: OSC0 */
#define BOARD_EXTAL0_SIGNAL EXTAL0 /*!<@brief OSC0 signal: EXTAL0 */
#define BOARD_EXTAL0_PORT PORTA /*!<@brief PORT device name: PORTA */
#define BOARD_EXTAL0_PIN 18U /*!<@brief PORTA pin index: 18 */
#define BOARD_EXTAL0_PIN_NAME EXTAL0 /*!<@brief Pin name */
#define BOARD_EXTAL0_LABEL "EXTAL_32KHZ" /*!<@brief Label */
#define BOARD_EXTAL0_NAME "EXTAL0" /*!<@brief Identifier name */
/* @} */
/*! @name PORTA19 (number 33), XTAL_32KHZ
@{ */
#define BOARD_XTAL0_PERIPHERAL OSC0 /*!<@brief Device name: OSC0 */
#define BOARD_XTAL0_SIGNAL XTAL0 /*!<@brief OSC0 signal: XTAL0 */
#define BOARD_XTAL0_PORT PORTA /*!<@brief PORT device name: PORTA */
#define BOARD_XTAL0_PIN 19U /*!<@brief PORTA pin index: 19 */
#define BOARD_XTAL0_PIN_NAME XTAL0 /*!<@brief Pin name */
#define BOARD_XTAL0_LABEL "XTAL_32KHZ" /*!<@brief Label */
#define BOARD_XTAL0_NAME "XTAL0" /*!<@brief Identifier name */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitOSC(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/