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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
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11
Living_SDK/board/developerkit/aos/atcmd_config_platform.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef _ATCMD_CONFIG_PLATFORM_H_
#define _ATCMD_CONFIG_PLATFORM_H_
// AT uart
#define AT_UART_PORT 3
#endif

40
Living_SDK/board/developerkit/aos/board.c Normal file
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#include "hal/soc/soc.h"
#include <aos/kernel.h>
/* Logic partition on flash devices */
hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX];
static void board_partition_init()
{
hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_APPLICATION].partition_description = "Application";
hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = 0x08000000;
hal_partitions[HAL_PARTITION_APPLICATION].partition_length = 0x3C000; //240k bytes
hal_partitions[HAL_PARTITION_APPLICATION].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = "PARAMETER1";
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = 0x0803C000;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = 0x1000; // 4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = "PARAMETER2";
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = 0x0803D000;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = 0x2000; //8k bytes
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_description = "PARAMETER4";
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_start_addr = 0x0803F000;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
}
void board_init(void)
{
board_partition_init();
board_cli_init();
}

10
Living_SDK/board/developerkit/aos/board.h Normal file
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#define HARDWARE_REVISION "V1.0"
#define MODEL "STM32L4"
#ifdef BOOTLOADER
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#else
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#endif

217
Living_SDK/board/developerkit/aos/board_cli.c Normal file
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#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <aos/aos.h>
#include <atparser.h>
#define STARTERKIT_WIFI_MODULE_FOTA "AT+FOTA"
#define FOTA_OOB_PREFIX "+FOTAEVENT:"
#define FOTA_OOB_POSTFIX "\r\n"
typedef struct modulefotastatus {
int ret;
aos_sem_t stmoduelfotasem;
} fotastatus_t;
static fotastatus_t fota_status;
static int module_fota_firmware_size_check(char *pcsize)
{
int i = 0;
if (NULL == pcsize){
printf("invalid input at $s %d \r\n", __FILE__, __LINE__);
return -1;
}
/*It's impossible that the size of firmware can over 10e9*/
if (strlen(pcsize) > 10) {
printf("invalid lenth %s at %s %d \r\n ", pcsize, __FILE__, __LINE__);
return -1;
}
for (i = 0; i < strlen(pcsize); i++){
if (pcsize[i] < '0' || pcsize[i] > '9'){
printf("invalid lenth %s at %s %d \r\n ", pcsize, __FILE__, __LINE__);
return -1;
}
}
return 0;
}
static int module_fota_firmware_md5_check(char *pcmd5)
{
int i = 0;
if (NULL == pcmd5){
printf("invalid input at $s %d \r\n", __FILE__, __LINE__);
return -1;
}
/*It's impossible that the length of md5 value can over 64*/
if (strlen(pcmd5) > 64) {
printf("invalid lenth %s at %s %d \r\n ", pcmd5, __FILE__, __LINE__);
return -1;
}
for (i = 0; i < strlen(pcmd5); i++){
if (!((pcmd5[i] >= '0' && pcmd5[i] <= '9')
|| (pcmd5[i] >= 'a' && pcmd5[i] <= 'f')
|| (pcmd5[i] >= 'A' && pcmd5[i] <= 'F'))){
printf("invalid lenth %s at %s %d \r\n ", pcmd5, __FILE__, __LINE__);
return -1;
}
}
return 0;
}
static int wifi_module_fota(char *pcsize, char *pcversion, char *pcurl, char *pcmd5)
{
char *pcatcmd = NULL;
char out[64] = {0};
int cmdlen = 0;
int ret = 0;
if (NULL == pcsize || NULL == pcversion || NULL == pcurl || NULL == pcmd5){
printf("invalid input at %s %d \r\n", __FILE__, __LINE__);
return -1;
}
pcatcmd = aos_malloc(1024);
if (NULL == pcatcmd){
printf("fail to malloc memory at %s %d \r\n", __FILE__, __LINE__);
return -1;
}
memset(pcatcmd, 0, 1024);
cmdlen = snprintf(pcatcmd, 1024, "%s=%s,%s,%s,%s", STARTERKIT_WIFI_MODULE_FOTA, pcsize,
pcversion, pcurl, pcmd5);
if (cmdlen >= 1024){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
ret = -1;
goto end;
}
ret = at.send_raw(pcatcmd, out, sizeof(out));
LOGD(TAG, "The AT response is: %s", out);
if (strstr(out, AT_RECV_FAIL_POSTFIX) != NULL || ret != 0) {
printf("%s %d failed", __func__, __LINE__);
ret = -1;
goto end;
}
aos_sem_wait(&fota_status.stmoduelfotasem , AOS_WAIT_FOREVER);
if (fota_status.ret != 0){
printf("module fota failed at %s %d \r\n", __FILE__, __LINE__);
ret = -1;
}
end:
aos_free(pcatcmd);
return ret;
}
static void handle_module_fota_cmd(char *pwbuf, int blen, int argc, char **argv)
{
int ret = 0;
char *pcsize = NULL;
char *pcversion = NULL;
char *pcurl = NULL;
char *pcmd5 = NULL;
if (argc != 5 || NULL == argv){
aos_cli_printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
pcsize = argv[1];
/*or check if atoi(pcsize) <= 0, is invalid*/
if (module_fota_firmware_size_check(pcsize) != 0){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
pcversion = argv[2];
if (strlen(pcversion) >= 64){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
pcurl = argv[3];
if (strlen(pcversion) >= 512){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
pcmd5 = argv[4];
if (module_fota_firmware_md5_check(pcmd5) != 0){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
printf("It's going to start wifi module fota it will cost several minutes. Please be patient, and Do not power off the module or reboot befor ota is finished. \r\n");
ret = wifi_module_fota(pcsize, pcversion, pcurl, pcmd5);
if (ret != 0){
printf("module-ota excute failed \r\n");
}else{
printf("module-ota excute successed \r\n");
}
return;
}
struct cli_command module_ota_cli_cmd[] = {
{
.name = "module-ota",
.help = "module-ota size version url md5-value",
.function = handle_module_fota_cmd
}
};
void fota_event_handler(void *arg, char *buf, int buflen)
{
int ret = -1;
if (NULL == buf || 0 == buflen){
printf("invalid input %s %d \r\n", __FILE__, __LINE__);
goto end;
}
if (strstr(buf, AT_RECV_FAIL_POSTFIX) != NULL){
printf("module-fota result is %s \r\n", buf);
goto end;
}
ret = 0;
end:
fota_status.ret = ret;
aos_sem_signal(&fota_status.stmoduelfotasem);
}
static void wifi_event_handler(input_event_t *event, void *priv_data)
{
if (event->type != EV_WIFI)
return;
if (event->code == CODE_WIFI_ON_GOT_IP){
at.oob(FOTA_OOB_PREFIX, FOTA_OOB_POSTFIX, 64, fota_event_handler, NULL);
aos_cli_register_commands(&module_ota_cli_cmd[0],sizeof(module_ota_cli_cmd) / sizeof(struct cli_command));
LOG("Hello, WiFi GOT_IP event! at %s %d\r\n", __FILE__, __LINE__);
}
}
int board_cli_init(void)
{
int ret = 0;
ret = aos_sem_new(&fota_status.stmoduelfotasem, 0);
if (ret){
printf("fail to creat sem4 %s %d \r\n", __FILE__, __LINE__);
}
fota_status.ret = 0;
aos_register_event_filter(EV_WIFI, wifi_event_handler, NULL);
}

229
Living_SDK/board/developerkit/aos/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 0
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 100
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#ifndef RHINO_CONFIG_SYSTEM_STACK_SIZE
#define RHINO_CONFIG_SYSTEM_STACK_SIZE 0x400
#endif
#endif /* CONFIG_H */

177
Living_SDK/board/developerkit/aos/soc_init.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <stdint.h>
#include "hal/hal.h"
#include "k_config.h"
#include "soc_init.h"
#define main st_main
#include "Src/main.c"
#if defined (__CC_ARM) && defined(__MICROLIB)
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#define GETCHAR_PROTOTYPE int fgetc(FILE *f)
size_t g_iram1_start = 0x20000000;
size_t g_iram1_total_size = 0x00040000;
#elif defined(__ICCARM__)
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#define GETCHAR_PROTOTYPE int fgetc(FILE *f)
#else
/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
set to 'Yes') calls __io_putchar() */
#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
#define GETCHAR_PROTOTYPE int __io_getchar(void)
#endif /* defined (__CC_ARM) && defined(__MICROLIB) */
uart_dev_t uart_0;
static void stduart_init(void);
static void brd_peri_init(void);
static void MX_SPI1_Init(void);
static void MX_SAI1_Init(void);
static void MX_CRC_Init(void);
static void MX_DMA_Init(void);
void stm32_soc_init(void)
{
HAL_Init();
/* Configure the system clock */
SystemClock_Config();
/**Configure the Systick interrupt time
*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/RHINO_CONFIG_TICKS_PER_SECOND);
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 0x0f, 0);
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*default uart init*/
stduart_init();
//brd_peri_init();
//MX_DMA_Init();
//MX_SAI1_Init();
//MX_SPI1_Init();
//MX_CRC_Init();
}
static void stduart_init(void)
{
uart_0.port = STDIO_UART;
uart_0.config.baud_rate = 115200;
uart_0.config.data_width = DATA_WIDTH_8BIT;
uart_0.config.flow_control = FLOW_CONTROL_DISABLED;
uart_0.config.mode = MODE_TX_RX;
uart_0.config.parity = NO_PARITY;
uart_0.config.stop_bits = STOP_BITS_1;
hal_uart_init(&uart_0);
}
static gpio_irq_trigger_t mode_rising = IRQ_TRIGGER_RISING_EDGE;
static gpio_irq_trigger_t mode_falling = IRQ_TRIGGER_FALLING_EDGE;
static gpio_irq_trigger_t mode_both = IRQ_TRIGGER_BOTH_EDGES;
static uint8_t gpio_set = 1;
static uint8_t gpio_reset = 0;
gpio_dev_t brd_gpio_table[] = {
{ALS_INT, IRQ_MODE, &mode_rising}, //PB8
{AUDIO_EN, OUTPUT_PUSH_PULL, &gpio_set}, //PA8
{LCD_DCX, OUTPUT_PUSH_PULL, &gpio_reset}, //PB1
{LCD_PWR, OUTPUT_PUSH_PULL, &gpio_reset}, //PA0
{LCD_RST, OUTPUT_PUSH_PULL, &gpio_set}, //PA1
{LED_ALS, OUTPUT_PUSH_PULL, &gpio_set}, //PB5
{LED_GS, OUTPUT_PUSH_PULL, &gpio_set}, //PB2
{LED_HTS, OUTPUT_PUSH_PULL, &gpio_set}, //PA15
{LED_PS, OUTPUT_PUSH_PULL, &gpio_set}, //PA12
{SW_FUNC_A, IRQ_MODE, &mode_rising}, //PA11
{SW_FUNC_B, IRQ_MODE, &mode_rising}, //PC13
{SW_WIFI, IRQ_MODE, &mode_rising}, //PB0
{WIFI_RST, OUTPUT_PUSH_PULL, &gpio_set}, //PB4
{WIFI_WU, OUTPUT_PUSH_PULL, &gpio_set}, //PB9
};
i2c_dev_t brd_i2c1_dev = {AOS_PORT_I2C1, {0}, NULL};
i2c_dev_t brd_i2c2_dev = {AOS_PORT_I2C2, {0}, NULL};
static void brd_peri_init(void)
{
int i;
int gpcfg_num = sizeof(brd_gpio_table) / sizeof(brd_gpio_table[0]);
for (i = 0; i < gpcfg_num; ++i) {
hal_gpio_init(&brd_gpio_table[i]);
}
hal_i2c_init(&brd_i2c1_dev);
hal_i2c_init(&brd_i2c2_dev);
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
HAL_IncTick();
krhino_intrpt_enter();
krhino_tick_proc();
krhino_intrpt_exit();
}
void HardFault_Handler(void)
{
while (1)
{
//#ifdef exc_print
// cpu_hardfault_handle();
// #endif
}
}
/**
* @brief Retargets the C library printf function to the USART.
* @param None
* @retval None
*/
PUTCHAR_PROTOTYPE
{
if (ch == '\n') {
//hal_uart_send(&console_uart, (void *)"\r", 1, 30000);
hal_uart_send(&uart_0, (void *)"\r", 1, 30000);
}
hal_uart_send(&uart_0, &ch, 1, 30000);
return ch;
}
/**
* @brief Retargets the C library scanf function to the USART.
* @param None
* @retval None
*/
GETCHAR_PROTOTYPE
{
/* Place your implementation of fgetc here */
/* e.g. readwrite a character to the USART2 and Loop until the end of transmission */
uint8_t ch = EOF;
int32_t ret = -1;
uint32_t recv_size;
ret = hal_uart_recv_II(&uart_0, &ch, 1, &recv_size, HAL_WAIT_FOREVER);
if (ret == 0) {
return ch;
} else {
return -1;
}
}

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Living_SDK/board/developerkit/aos/soc_init.h Normal file
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/**
******************************************************************************
* File Name : main.hpp
* Description : This file contains the common defines of the application
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SOC_INIT_H
#define __SOC_INIT_H
/* Includes ------------------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "hal/hal.h"
#include "hal/hal_gpio_stm32l4.h"
#include "hal/hal_i2c_stm32l4.h"
#include "hal/hal_uart_stm32l4.h"
/* USER CODE END Includes */
/* Private define ------------------------------------------------------------*/
typedef enum {
GPIO_ALS_INT,
GPIO_AUDIO_EN,
GPIO_LCD_DCX,
GPIO_LCD_PWR,
GPIO_LCD_RST,
GPIO_LED_ALS,
GPIO_LED_GS,
GPIO_LED_HTS,
GPIO_LED_PS,
GPIO_SW_FUNC_A,
GPIO_SW_FUNC_B,
GPIO_SW_WIFI,
GPIO_WIFI_RST,
GPIO_WIFI_WU,
MAX_GPIO_NUM
} BOARD_GPIO;
extern gpio_dev_t brd_gpio_table[];
extern i2c_dev_t brd_i2c1_dev;
extern i2c_dev_t brd_i2c2_dev;
extern uart_dev_t brd_uart1_dev;
/* legency definition for the modules have no hal layer */
#define SW_FUNC_B_Pin GPIO_PIN_13
#define SW_FUNC_B_GPIO_Port GPIOC
#define SW_FUNC_B_EXTI_IRQn EXTI15_10_IRQn
#define LCD_PWR_Pin GPIO_PIN_0
#define LCD_PWR_GPIO_Port GPIOA
#define LCD_RST_Pin GPIO_PIN_1
#define LCD_RST_GPIO_Port GPIOA
#define LCD_NSS_Pin GPIO_PIN_4
#define LCD_NSS_GPIO_Port GPIOA
#define LCD_SCK_Pin GPIO_PIN_5
#define LCD_SCK_GPIO_Port GPIOA
#define LCD_TX_Pin GPIO_PIN_7
#define LCD_TX_GPIO_Port GPIOA
#define SW_WIFI_Pin GPIO_PIN_0
#define SW_WIFI_GPIO_Port GPIOB
#define SW_WIFI_EXTI_IRQn EXTI0_IRQn
#define LCD_DCX_Pin GPIO_PIN_1
#define LCD_DCX_GPIO_Port GPIOB
#define LED_GS_Pin GPIO_PIN_2
#define LED_GS_GPIO_Port GPIOB
#define AUDIO_EN_Pin GPIO_PIN_8
#define AUDIO_EN_GPIO_Port GPIOA
#define SW_FUNC_A_Pin GPIO_PIN_11
#define SW_FUNC_A_GPIO_Port GPIOA
#define SW_FUNC_A_EXTI_IRQn EXTI15_10_IRQn
#define LED_PS_Pin GPIO_PIN_12
#define LED_PS_GPIO_Port GPIOA
#define LED_HTS_Pin GPIO_PIN_15
#define LED_HTS_GPIO_Port GPIOA
#define WIFI_RST_Pin GPIO_PIN_4
#define WIFI_RST_GPIO_Port GPIOB
#define LED_ALS_Pin GPIO_PIN_5
#define LED_ALS_GPIO_Port GPIOB
#define WIFI_TX_Pin GPIO_PIN_6
#define WIFI_TX_GPIO_Port GPIOB
#define WIFI_RX_Pin GPIO_PIN_7
#define WIFI_RX_GPIO_Port GPIOB
#define ALS_INT_Pin GPIO_PIN_8
#define ALS_INT_GPIO_Port GPIOB
#define ALS_INT_EXTI_IRQn EXTI9_5_IRQn
#define WIFI_WU_Pin GPIO_PIN_9
#define WIFI_WU_GPIO_Port GPIOB
#define B1_Pin GPIO_PIN_13
#define B1_GPIO_Port GPIOC
#define MCO_Pin GPIO_PIN_0
#define MCO_GPIO_Port GPIOH
#define USART_RX_Pin GPIO_PIN_3
#define USART_RX_GPIO_Port GPIOA
#define LD4_Pin GPIO_PIN_5
#define LD4_GPIO_Port GPIOA
#define SMPS_EN_Pin GPIO_PIN_12
#define SMPS_EN_GPIO_Port GPIOB
#define SMPS_V1_Pin GPIO_PIN_13
#define SMPS_V1_GPIO_Port GPIOB
#define SMPS_PG_Pin GPIO_PIN_14
#define SMPS_PG_GPIO_Port GPIOB
#define SPMS_SW_Pin GPIO_PIN_15
#define SPMS_SW_GPIO_Port GPIOB
#define TMS_Pin GPIO_PIN_13
#define TMS_GPIO_Port GPIOA
#define TCK_Pin GPIO_PIN_14
#define TCK_GPIO_Port GPIOA
#define SWO_Pin GPIO_PIN_3
#define SWO_GPIO_Port GPIOB
#define LCD_DCX_Pin GPIO_PIN_1
#define LCD_DCX_GPIO_Port GPIOB
#define LCD_PWR_Pin GPIO_PIN_0
#define LCD_PWR_GPIO_Port GPIOA
#define LCD_RST_Pin GPIO_PIN_1
#define LCD_RST_GPIO_Port GPIOA
#define LCD_NSS_Pin GPIO_PIN_4
#define LCD_NSS_GPIO_Port GPIOA
#define LCD_SCK_Pin GPIO_PIN_5
#define LCD_SCK_GPIO_Port GPIOA
#define LCD_TX_Pin GPIO_PIN_7
#define LCD_TX_GPIO_Port GPIOA
#define KIDS_A10_PRT(fmt, args...) \
printf("%s: [%s-->%d]=> "fmt, \
__FILE__, __FUNCTION__, \
__LINE__, ##args)
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
extern "C" {
#endif
void _Error_Handler(char *, int);
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* __SOC_INIT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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#include <stdlib.h>
#include <string.h>
#include "stm32l4xx_hal.h"
#include "soc_init.h"
#include "st7789.h"
extern SPI_HandleTypeDef hspi1;
static SPI_HandleTypeDef *hspi_lcd = NULL;
static struct st7789_function st7789_cfg_script[] = {
{ST7789_START, ST7789_START},
{ST7789_CMD, 0x11},
{ST7789_DELAY, 120},
{ST7789_CMD, 0x36},
{ST7789_DATA, 0x00},
{ST7789_CMD, 0x3a},
{ST7789_DATA, 0x05},
{ST7789_CMD, 0xb2},
{ST7789_DATA, 0x0c},
{ST7789_DATA, 0x0c},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x33},
{ST7789_DATA, 0x33},
{ST7789_CMD, 0xb7},
{ST7789_DATA, 0x72},
{ST7789_CMD, 0xbb},
{ST7789_DATA, 0x3d},
{ST7789_CMD, 0xc2},
{ST7789_DATA, 0x01},
{ST7789_CMD, 0xc3},
{ST7789_DATA, 0x19},
{ST7789_CMD, 0xc4},
{ST7789_DATA, 0x20},
{ST7789_CMD, 0xc6},
{ST7789_DATA, 0x0f},
{ST7789_CMD, 0xd0},
{ST7789_DATA, 0xa4},
{ST7789_DATA, 0xa1},
{ST7789_CMD, 0xe0},
{ST7789_DATA, 0x70},
{ST7789_DATA, 0x04},
{ST7789_DATA, 0x08},
{ST7789_DATA, 0x09},
{ST7789_DATA, 0x09},
{ST7789_DATA, 0x05},
{ST7789_DATA, 0x2a},
{ST7789_DATA, 0x33},
{ST7789_DATA, 0x41},
{ST7789_DATA, 0x07},
{ST7789_DATA, 0x13},
{ST7789_DATA, 0x13},
{ST7789_DATA, 0x29},
{ST7789_DATA, 0x2f},
{ST7789_CMD, 0xe1},
{ST7789_DATA, 0x70},
{ST7789_DATA, 0x03},
{ST7789_DATA, 0x09},
{ST7789_DATA, 0x0a},
{ST7789_DATA, 0x09},
{ST7789_DATA, 0x06},
{ST7789_DATA, 0x2b},
{ST7789_DATA, 0x34},
{ST7789_DATA, 0x41},
{ST7789_DATA, 0x07},
{ST7789_DATA, 0x12},
{ST7789_DATA, 0x14},
{ST7789_DATA, 0x28},
{ST7789_DATA, 0x2e},
{ST7789_CMD, 0x21},
{ST7789_CMD, 0x29},
{ST7789_CMD, 0x2a},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0xef},
{ST7789_CMD, 0x2b},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0xef},
{ST7789_CMD, 0x2c},
{ST7789_END, ST7789_END},
};
static HAL_StatusTypeDef st7789_write(int is_cmd, uint8_t data)
{
uint8_t pData[2] = {0};
if (hspi_lcd == NULL) {
_Error_Handler(__FILE__, __LINE__);
return HAL_ERROR;
}
pData[0] = data;
#ifdef ALIOS_HAL
if (is_cmd)
hal_gpio_output_low(&brd_gpio_table[GPIO_LCD_DCX]);
else
hal_gpio_output_high(&brd_gpio_table[GPIO_LCD_DCX]);
#else
if (is_cmd)
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_RESET);
else
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_SET);
#endif
return HAL_SPI_Transmit(hspi_lcd, pData, 1, HAL_MAX_DELAY);
}
static HAL_StatusTypeDef st7789_write_fb(uint16_t *data, uint16_t size)
{
if (hspi_lcd == NULL) {
_Error_Handler(__FILE__, __LINE__);
return HAL_ERROR;
}
return HAL_SPI_Transmit(hspi_lcd, (uint8_t *)data, size, HAL_MAX_DELAY);
}
static void st7789_run_cfg_script()
{
uint8_t data[2] = {0};
int i = 0;
int end_script = 0;
do {
switch (st7789_cfg_script[i].cmd) {
case ST7789_START:
break;
case ST7789_CMD:
data[0] = st7789_cfg_script[i].data & 0xff;
st7789_write(1, data[0]);
break;
case ST7789_DATA:
data[0] = st7789_cfg_script[i].data & 0xff;
st7789_write(0, data[0]);
break;
case ST7789_DELAY:
krhino_task_sleep(krhino_ms_to_ticks(st7789_cfg_script[i].data));
break;
case ST7789_END:
end_script = 1;
}
i++;
} while (!end_script);
}
static void st7789_reset()
{
#ifdef ALIOS_HAL
hal_gpio_output_high(&brd_gpio_table[GPIO_LCD_PWR]);
hal_gpio_output_high(&brd_gpio_table[GPIO_LCD_RST]);
krhino_task_sleep(krhino_ms_to_ticks(50));
hal_gpio_output_low(&brd_gpio_table[GPIO_LCD_RST]);
krhino_task_sleep(krhino_ms_to_ticks(50));
hal_gpio_output_high(&brd_gpio_table[GPIO_LCD_RST]);
krhino_task_sleep(krhino_ms_to_ticks(150));
#else
HAL_GPIO_WritePin(LCD_PWR_GPIO_Port, LCD_PWR_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_SET);
HAL_Delay(50);
/* Reset controller */
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_RESET);
HAL_Delay(50);
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_SET);
HAL_Delay(150);
#endif
}
#if 0
static void st7789_set_addr_win(uint16_t xs, uint16_t ys, uint16_t xe, uint16_t ye)
{
uint8_t col_data[4] = {0};
uint8_t row_data[4] = {0};
col_data[0] = xs >> 8 & 0xff;
col_data[1] = xs & 0xff;
col_data[2] = xe >> 8 & 0xff;
col_data[3] = xe & 0xff;
row_data[0] = ys >> 8 & 0xff;
row_data[1] = ys & 0xff;
row_data[2] = ye >> 8 & 0xff;
row_data[3] = ye & 0xff;
st7789_write(1, ST7789_CASET);
st7789_write(0, col_data[0]);
st7789_write(0, col_data[1]);
st7789_write(0, col_data[2]);
st7789_write(0, col_data[3]);
st7789_write(1, ST7789_RASET);
st7789_write(0, row_data[0]);
st7789_write(0, row_data[1]);
st7789_write(0, row_data[2]);
st7789_write(0, row_data[3]);
}
#define LCD_MAX_MEM16_BLOCK (1 << 6)
#define LCD_PIXEL_PER_BLOCK (LCD_MAX_MEM16_BLOCK >> 1)
static void spec_send_fb(uint16_t color, uint16_t pixel_num)
{
int i;
int count, remain;
uint16_t real_mem[LCD_MAX_MEM16_BLOCK] = {0};
for (i = 0; i < LCD_MAX_MEM16_BLOCK; ++i) {
real_mem[i] = color;
}
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_SET);
if (pixel_num <= LCD_MAX_MEM16_BLOCK) {
st7789_write_fb(real_mem, pixel_num << 1);
} else {
count = pixel_num / LCD_MAX_MEM16_BLOCK;
remain = pixel_num % LCD_MAX_MEM16_BLOCK;
for (i = 0; i < count; ++i) {
st7789_write_fb(real_mem, LCD_MAX_MEM16_BLOCK << 1);
}
st7789_write_fb(real_mem, remain << 1);
}
}
static void st7789_display_picture(void)
{
st7789_write(1, ST7789_RAMWR);
spec_send_fb(0x0, WIDTH * HEIGHT / 4);
spec_send_fb(0x1111, WIDTH * HEIGHT / 4);
spec_send_fb(0x7777, WIDTH * HEIGHT / 4);
spec_send_fb(0xeeee, WIDTH * HEIGHT / 4);
}
#endif
int st7789_init()
{
hspi_lcd = &hspi1;
st7789_reset();
st7789_run_cfg_script();
// st7789_display_picture();
return HAL_OK;
}
void ST7789H2_WriteReg(uint8_t Command, uint8_t *Parameters, uint8_t NbParameters)
{
uint8_t i;
/* Send command */
LcdWriteReg(Command);
/* Send command's parameters if any */
for (i=0; i<NbParameters; i++)
{
LcdWriteData(Parameters[i]);
}
}
void ST7789H2_SetCursor(uint16_t Xpos, uint16_t Ypos)
{
uint8_t parameter[4];
/* CASET: Comumn Addrses Set */
parameter[0] = 0x00;
parameter[1] = 0x00 + Xpos;
parameter[2] = 0x00;
parameter[3] = 0xEF + Xpos;
ST7789H2_WriteReg(0x2A, parameter, 4);
/* RASET: Row Addrses Set */
parameter[0] = 0x00;
parameter[1] = 0x00 + Ypos;
parameter[2] = 0x00;
parameter[3] = 0xEF + Ypos;
ST7789H2_WriteReg(0x2B, parameter, 4);
}
uint8_t black_gui[480] = {0};
void BSP_LCD_Clear(uint16_t Color)
{
uint32_t counter = 0;
uint32_t y_size = 0;
memset(black_gui, 0xFF, sizeof(black_gui));
for (counter = 0; counter < 240; counter++)
{
/* Set Cursor */
ST7789H2_SetCursor(0, counter);
/* Prepare to write to LCD RAM */
ST7789H2_WriteReg(0x2C, (uint8_t*)NULL, 0); /* RAM write data command */
LcdWriteDataMultiple(black_gui, 480);
}
}
void ST7789H2_WritePixel(uint16_t Xpos, uint16_t Ypos, uint16_t RGBCode)
{
/* Set Cursor */
ST7789H2_SetCursor(Xpos, Ypos);
/* Prepare to write to LCD RAM */
ST7789H2_WriteReg(0x2C, (uint8_t*)NULL, 0); /* RAM write data command */
/* Write RAM data */
LcdWriteDataMultiple(&RGBCode, 2);
}
void LcdWriteReg(uint8_t Data)
{
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi1, &Data, 1, 10);
}
void LcdWriteData(uint8_t Data)
{
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_SET);
HAL_SPI_Transmit(&hspi1, &Data, 1, 10);
}
void LcdWriteDataMultiple(uint8_t * pData, int NumItems)
{
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_SET);
HAL_SPI_Transmit(&hspi1, pData, NumItems, 10);
}

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#ifndef __ST7789_H
#define __ST7789_H
#define WIDTH 240
#define HEIGHT 240
#define BPP 16
/* Init script function */
struct st7789_function {
uint8_t cmd;
uint16_t data;
};
/* Init script commands */
enum st7789_cmd {
ST7789_START,
ST7789_END,
ST7789_CMD,
ST7789_DATA,
ST7789_DELAY
};
/* ST7789 Commands */
#define ST7789_CASET 0x2A
#define ST7789_RASET 0x2B
#define ST7789_RAMWR 0x2C
#define ST7789_RAMRD 0x2E
int st7789_init();
void LcdWriteReg(uint8_t Data);
void LcdWriteData(uint8_t Data);
void LcdWriteDataMultiple(uint8_t * pData, int NumItems);
#endif /* __ST7789_H */