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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
commit 27b3e2883d
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11
Living_SDK/board/b_l475e/atcmd_config_platform.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef _ATCMD_CONFIG_PLATFORM_H_
#define _ATCMD_CONFIG_PLATFORM_H_
// AT uart
#define AT_UART_PORT 1
#endif

58
Living_SDK/board/b_l475e/b_l475e.mk Normal file
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NAME := board_b_l475e
JTAG := stlink-v2-1
$(NAME)_TYPE := kernel
MODULE := 1062
HOST_ARCH := Cortex-M4
HOST_MCU_FAMILY := stm32l475
SUPPORT_BINS := no
$(NAME)_SOURCES := board.c osa_flash.c
GLOBAL_INCLUDES += .
GLOBAL_DEFINES += STDIO_UART=0
GLOBAL_DEFINES += RHINO_CONFIG_TICK_TASK=0
GLOBAL_DEFINES += RHINO_CONFIG_WORKQUEUE=1
sal ?= 1
ifeq (1,$(sal))
$(NAME)_COMPONENTS += sal
module ?= wifi.mk3060
else
GLOBAL_DEFINES += CONFIG_NO_TCPIP
endif
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_B-L475E
CONFIG_SYSINFO_DEVICE_NAME := B-L475E
GLOBAL_CFLAGS += -DSYSINFO_OS_VERSION=\"$(CONFIG_SYSINFO_OS_VERSION)\"
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
ifeq ($(COMPILER),armcc)
else ifeq ($(COMPILER),iar)
else
GLOBAL_LDFLAGS += -L $(SOURCE_ROOT)/board/b_l475e
endif
# Global defines
# HSE_VALUE = STM32 crystal frequency = 26MHz (needed to make UART work correctly)
GLOBAL_DEFINES += $$(if $$(NO_CRLF_STDIO_REPLACEMENT),,CRLF_STDIO_REPLACEMENT)
GLOBAL_CFLAGS += -DSTM32L475xx
WIFI_FIRMWARE_SECTOR_START := 2 #0x2000
FILESYSTEM_IMAGE_SECTOR_START := 256 #0x100000
# Extra build target in mico_standard_targets.mk, include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
EXTRA_TARGET_MAKEFILES += $(MAKEFILES_PATH)/aos_standard_targets.mk
#EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk
# Define default component testcase for certification
ifneq (, $(findstring yts, $(BUILD_STRING)))
TEST_COMPONENTS += basic rhino yloop api kv
TEST_COMPONENTS += cjson list digest_algorithm hashtable
TEST_COMPONENTS += netmgr wifi_hal
TEST_COMPONENTS += http cloudcoap
endif

44
Living_SDK/board/b_l475e/board.c Executable file
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#include "hal/soc/soc.h"
#include <aos/kernel.h>
/* Logic partition on flash devices */
hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX];
void board_init(void)
{
hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_APPLICATION].partition_description = "Application";
hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = 0x08000000;
hal_partitions[HAL_PARTITION_APPLICATION].partition_length = 0x7D000; //500k bytes
hal_partitions[HAL_PARTITION_APPLICATION].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = "PARAMETER1";
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = 0x0807D000;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = 0x1000; // 4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = "PARAMETER2";
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = 0x0807E000;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_description = "OTA Storage";
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_start_addr = 0x08080000;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_length = 0x7D000; //500k bytes
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_description = "PARAMETER3";
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_start_addr = 0x080FD000;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_description = "PARAMETER4";
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_start_addr = 0x080FE000;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
}

10
Living_SDK/board/b_l475e/board.h Normal file
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#define HARDWARE_REVISION "V1.0"
#define MODEL "STM32L4"
#ifdef BOOTLOADER
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#else
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#endif

225
Living_SDK/board/b_l475e/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 0
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 100
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#endif /* CONFIG_H */

493
Living_SDK/board/b_l475e/osa_flash.c Normal file
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#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "stm32l4xx_hal.h"
#include "stm32l4xx_hal_flash.h"
#define EN_DBG 0
#define KM_FLASH_ADDR_START 0x080FF000
#define KM_FLASH_ADDR_SIZE 0x1000
#define FLASH_BLOCK_LEN FLASH_PAGE_SIZE
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t Addr)
{
uint32_t page = 0;
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
/* Bank 1 */
page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE;
}
else
{
/* Bank 2 */
page = (Addr - (FLASH_BASE + FLASH_BANK_SIZE)) / FLASH_PAGE_SIZE;
}
return page;
}
/**
* @brief Gets the bank of a given address
* @param Addr: Address of the FLASH Memory
* @retval The bank of a given address
*/
static uint32_t GetBank(uint32_t Addr)
{
uint32_t bank = 0;
if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
{
/* No Bank swap */
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
bank = FLASH_BANK_1;
}
else
{
bank = FLASH_BANK_2;
}
}
else
{
/* Bank swap */
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
bank = FLASH_BANK_2;
}
else
{
bank = FLASH_BANK_1;
}
}
return bank;
}
int32_t osa_flash_read(void *addr, void *out, size_t size)
{
#if EN_DBG
printf("flash read addr 0x%08x size 0x%08x\n", (uint32_t)addr, size);
#endif
memcpy(out, addr ,size);
#if EN_DBG
printf("data 0x%02x 0x%02x 0x%02x 0x%02x\n",
*((uint8_t *)out + 0), *((uint8_t *)out + 1),
*((uint8_t *)out + 2), *((uint8_t *)out + 3));
#endif
return 0;
}
int32_t osa_flash_write(void *addr, void *buf, size_t size)
{
uint64_t *p = (uint64_t *)buf;
uint32_t a = (uint32_t)addr;
HAL_StatusTypeDef ret = HAL_OK;
if (0 != ((uint32_t)addr % 8) || 0 != (size % 8)) {
printf("bad param addr 0x%08x size 0x%08x\n",
(unsigned int)addr , (unsigned int)size);
return -1;
}
#if EN_DBG
printf("flash write addr 0x%08x size 0x%08x\n",
(uint32_t)addr , (uint32_t)size);
#endif
HAL_FLASH_Unlock();
while ((size >= 8) && (ret == HAL_OK)) {
ret = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, (uint32_t)a, (uint64_t)(*p));
if (0 != ret) {
printf("write flash fail addr %08x data %llx ret 0x%08x\n",
(unsigned int)a, (uint64_t)(*p), (unsigned int)ret);
return -1;
}
#if EN_DBG
uint8_t tmp_buf[8];
int i;
osa_flash_read((void *)a , tmp_buf, 8);
if (0 != memcmp(tmp_buf, p, 8)) {
printf("write than read not match \n");
for (i = 0; i < 8; ++i) {
printf("write buf 0x%02x read data 0x%02x\n", *((uint8_t *)p + i), tmp_buf[i]);
}
return -1;
}
#if 0
for (i = 0; i < 8; ++i) {
printf("write buf 0x%02x read data 0x%02x\n", *((uint8_t *)p + i), tmp_buf[i]);
}
#endif
#endif
p = (uint64_t *)((uint32_t)p + 8);
a += 8;
size -= 8;
}
HAL_FLASH_Lock();
return 0;
}
int32_t osa_flash_erase(void *addr, size_t size)
{
uint32_t PageError = 0;
FLASH_EraseInitTypeDef pEraseInit;
uint32_t cur_addr = (uint32_t)addr;
size_t cur_size = size;
HAL_FLASH_Unlock();
if (0 != (size % FLASH_BLOCK_LEN) || 0 != (cur_addr % FLASH_BLOCK_LEN)) {
printf("bad param addr 0x%08x size 0x%08x\n",
(unsigned int)addr, (unsigned int)size);
return -1;
}
if (0 == size) {
return 0;
}
while (cur_size > 0) {
/* Fill EraseInit structure*/
pEraseInit.TypeErase = FLASH_TYPEERASE_PAGES;
pEraseInit.Banks = GetBank(cur_addr);
pEraseInit.Page = GetPage(cur_addr);
pEraseInit.NbPages = 1;
#if EN_DBG
printf("flash erase page %d bank %d\n", GetPage(cur_addr), GetBank(cur_addr));
#endif
if (HAL_FLASHEx_Erase(&pEraseInit, &PageError) != HAL_OK)
{
printf("flash erase fail\n");
return -1;
}
cur_size -= FLASH_BLOCK_LEN;
cur_addr -= FLASH_BLOCK_LEN;
}
HAL_FLASH_Lock();
return 0;
}
int32_t getRDPLevel(uint32_t *RDPLevel)
{
FLASH_OBProgramInitTypeDef sFlashOptionBytes;
int32_t eRetStatus = 0;
if (NULL == RDPLevel) {
return -1;
}
/* Unlock the Flash to enable the flash control register access
*************/
HAL_FLASH_Unlock();
/* Clear OPTVERR bit set on virgin samples */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
/* Unlock the Options Bytes
*************************************************/
HAL_FLASH_OB_Unlock();
/* Get Option Bytes status for FLASH_BANK_1: WRP AREA_A and PCRoP
**********/
HAL_FLASHEx_OBGetConfig(&sFlashOptionBytes);
*RDPLevel = sFlashOptionBytes.RDPLevel;
/* Lock the Options Bytes
***************************************************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
return eRetStatus;
}
int32_t ConfigWRP (bool enable, bool reboot)
{
int32_t eRetStatus = 0;
uint32_t RDPlevel;
uint32_t StartPage = 0, EndPage = 0, StartBank = 0, EndBank = 0;
FLASH_OBProgramInitTypeDef psFlashOptionBytes, psFlashOptionBytes2;
eRetStatus = getRDPLevel(&RDPlevel);
if (0 != eRetStatus) {
return -1;
}
if (OB_RDP_LEVEL_2 == RDPlevel) {
return -1;
}
/* Get the number of the start and end pages */
StartPage = GetPage(KM_FLASH_ADDR_START);
EndPage = GetPage(KM_FLASH_ADDR_START + KM_FLASH_ADDR_SIZE - 1);
/* Get the bank of the start and end pages */
StartBank = GetBank(KM_FLASH_ADDR_START);
EndBank = GetBank(KM_FLASH_ADDR_START + KM_FLASH_ADDR_SIZE - 1);
if (StartBank != EndBank) {
/* cross bank not support now */
return -1;
}
/* WRP area is only on one bank */
if (StartBank == FLASH_BANK_1)
{
psFlashOptionBytes.WRPArea = OB_WRPAREA_BANK1_AREAA;
psFlashOptionBytes2.WRPArea = OB_WRPAREA_BANK1_AREAB;
}
else
{
psFlashOptionBytes.WRPArea = OB_WRPAREA_BANK2_AREAA;
psFlashOptionBytes2.WRPArea = OB_WRPAREA_BANK2_AREAB;
}
HAL_FLASH_Unlock();
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
HAL_FLASH_OB_Unlock();
HAL_FLASHEx_OBGetConfig(&psFlashOptionBytes);
HAL_FLASHEx_OBGetConfig(&psFlashOptionBytes2);
if (true == enable) {
/* Check if desired pages are not yet write protected ***********************/
if ((psFlashOptionBytes.WRPStartOffset <= StartPage) && (psFlashOptionBytes.WRPEndOffset >= (StartPage - 1)))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes.WRPEndOffset < EndPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
}
else if ((psFlashOptionBytes.WRPStartOffset <= (EndPage + 1)) && (psFlashOptionBytes.WRPEndOffset >= EndPage))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes.WRPStartOffset > StartPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
}
}
else if ((psFlashOptionBytes.WRPStartOffset > StartPage) && (psFlashOptionBytes.WRPEndOffset < EndPage))
{
/* Current area is included in pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
else if ((psFlashOptionBytes2.WRPStartOffset <= StartPage) && (psFlashOptionBytes2.WRPEndOffset >= (StartPage - 1)))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes2.WRPEndOffset < EndPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset <= (EndPage + 1)) && (psFlashOptionBytes2.WRPEndOffset >= EndPage))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes2.WRPStartOffset > StartPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset > StartPage) && (psFlashOptionBytes2.WRPEndOffset < EndPage))
{
/* Current area is included in pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
else if (psFlashOptionBytes.WRPStartOffset > psFlashOptionBytes.WRPEndOffset)
{
/* Current area is not used => it will be configured to protect the pages */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
else if (psFlashOptionBytes2.WRPStartOffset > psFlashOptionBytes2.WRPEndOffset)
{
/* Current area is not used => it will be configured to protect the pages */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
else
{
/* No more area available to protect the pages */
/* => Error : not possible to activate the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
} else {
/* disable */
/* Check if desired pages are already write protected ***********************/
if ((psFlashOptionBytes.WRPStartOffset == StartPage) && (psFlashOptionBytes.WRPEndOffset == EndPage))
{
/* Current area correspond to the area to disable */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = 0xFF;
psFlashOptionBytes.WRPEndOffset = 0;
}
else if ((psFlashOptionBytes.WRPStartOffset == StartPage) && (psFlashOptionBytes.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable : */
/* - End of area is bigger than the last page to un-protect */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = EndPage + 1;
}
else if ((psFlashOptionBytes.WRPStartOffset < StartPage) && (psFlashOptionBytes.WRPEndOffset == EndPage))
{
/* Current area is bigger than the area to disable : */
/* - Start of area is lower than the first page to un-protect */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = StartPage - 1;
}
else if ((psFlashOptionBytes.WRPStartOffset < StartPage) && (psFlashOptionBytes.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable */
/* - Start of area is lower than the first page to un-protect */
/* - End of area is bigger than the last page to un-protect */
if (psFlashOptionBytes2.WRPStartOffset > psFlashOptionBytes2.WRPEndOffset)
{
/* Second area of the bank can be used */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = EndPage + 1;
psFlashOptionBytes2.WRPEndOffset = psFlashOptionBytes.WRPEndOffset;
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = StartPage - 1;
}
else
{
/* Second area of the bank already used for WRP */
/* => Error : not possible to deactivate only the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset == StartPage) && (psFlashOptionBytes2.WRPEndOffset == EndPage))
{
/* Current area correspond to the area to disable */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = 0xFF;
psFlashOptionBytes2.WRPEndOffset = 0;
}
else if ((psFlashOptionBytes2.WRPStartOffset == StartPage) && (psFlashOptionBytes2.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable : */
/* - End of area is bigger than the last page to un-protect */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = EndPage + 1;
}
else if ((psFlashOptionBytes2.WRPStartOffset < StartPage) && (psFlashOptionBytes2.WRPEndOffset == EndPage))
{
/* Current area is bigger than the area to disable : */
/* - Start of area is lower than the first page to un-protect */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = StartPage - 1;
}
else if ((psFlashOptionBytes2.WRPStartOffset < StartPage) && (psFlashOptionBytes2.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable */
/* - Start of area is lower than the first page to un-protect */
/* - End of area is bigger than the last page to un-protect */
if (psFlashOptionBytes.WRPStartOffset > psFlashOptionBytes.WRPEndOffset)
{
/* Second area of the bank can be used */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = EndPage + 1;
psFlashOptionBytes.WRPEndOffset = psFlashOptionBytes2.WRPEndOffset;
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = StartPage - 1;
}
else
{
/* Second area of the bank already used for WRP */
/* => Error : not possible to deactivate only the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
}
/* Configure write protected pages */
if (psFlashOptionBytes.OptionType == OPTIONBYTE_WRP)
{
if(HAL_FLASHEx_OBProgram(&psFlashOptionBytes) != HAL_OK)
{
/* Error occurred while options bytes programming. **********************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
if (psFlashOptionBytes2.OptionType == OPTIONBYTE_WRP)
{
if(HAL_FLASHEx_OBProgram(&psFlashOptionBytes2) != HAL_OK)
{
/* Error occurred while options bytes programming. **********************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
/* Generate System Reset to load the new option byte values ***************/
if (((psFlashOptionBytes.OptionType == OPTIONBYTE_WRP) || (psFlashOptionBytes2.OptionType == OPTIONBYTE_WRP)) && reboot)
{
HAL_FLASH_OB_Launch();
}
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
return eRetStatus;
}
int32_t CleanProtectionWRP (void)
{
int32_t eRetStatus = 0;
uint32_t RDPlevel;
FLASH_OBProgramInitTypeDef psFlashOptionBytes;
eRetStatus = getRDPLevel(&RDPlevel);
if (0 != eRetStatus) {
return -1;
}
if (OB_RDP_LEVEL_2 == RDPlevel) {
return -1;
}
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPArea = 0;//SFU_HAL_IF_PROTECT_WRP_AREA_1;
psFlashOptionBytes.WRPStartOffset = 0;
psFlashOptionBytes.WRPEndOffset = 0;
if (HAL_FLASHEx_OBProgram(&psFlashOptionBytes) != HAL_OK) {
eRetStatus = -1;
}
return eRetStatus;
}