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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
commit 27b3e2883d
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34
Living_SDK/board/amebaz_dev/amebaz_dev.mk Normal file
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NAME := board_amebaz_dev
JTAG := jlink_swd
$(NAME)_TYPE := kernel
MODULE := AmebaZ
HOST_ARCH := Cortex-M4
HOST_MCU_FAMILY := rtl8710bn
SUPPORT_BINS := no
$(NAME)_SOURCES := board.c
GLOBAL_INCLUDES += .
GLOBAL_DEFINES += STDIO_UART=0
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_AMEBAZ
CONFIG_SYSINFO_DEVICE_NAME := AMEBAZ
CONFIG_BOARD_NAME = AMEBAZ
$(info CONFIG_BOARD_NAME : $(CONFIG_BOARD_NAME))
GLOBAL_DEFINES += BOARD_NAME=AMEBAZ
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
#GLOBAL_CFLAGS += -DSYSINFO_KERNEL_VERSION=\"$(CONFIG_SYSINFO_KERNEL_VERSION)\"
#GLOBAL_CFLAGS += -DSYSINFO_APP_VERSION=\"$(CONFIG_SYSINFO_APP_VERSION)\"
#include $(SOURCE_ROOT)/board/rtl8710bn/export-rom_symbol_v01.txt
#GLOBAL_CFLAGS += -L $(SOURCE_ROOT)/board/amebaz_dev
# Extra build target in mico_standard_targets.mk, include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/download.mk
EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk

77
Living_SDK/board/amebaz_dev/board.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include "hal/soc/soc.h"
#include <aos/kernel.h>
#include <aos/aos.h>
/* Logic partition on flash devices */
const hal_logic_partition_t hal_partitions[] =
{
[HAL_PARTITION_BOOTLOADER] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Bootloader",
.partition_start_addr = 0x0,
.partition_length = 0x8000, //32k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS,
},
[HAL_PARTITION_APPLICATION] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Application",
.partition_start_addr = 0xB000,
.partition_length = 0xF2000, //568k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_1] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER1",
.partition_start_addr = 0xFD000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_2] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER2",
.partition_start_addr = 0xFE000,
.partition_length = 0x2000, // 8k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_OTA_TEMP] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "OTA Storage",
.partition_start_addr = 0x100000,
.partition_length = 0xF2000, //568k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_3] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER3",
.partition_start_addr = 0x1FD000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_4] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER4",
.partition_start_addr = 0x1FE000,
.partition_length = 0x2000,// 8k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
};
void board_init(void)
{
}

166
Living_SDK/board/amebaz_dev/board.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#define HARDWARE_REVISION "V1.0"
#define MODEL "AmebaZ"
#ifdef BOOTLOADER
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 921600
#else
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 921600
#endif
/******************************************************
* Macros
******************************************************/
/******************************************************
* Constants
******************************************************/
/******************************************************
* Enumerations
******************************************************/
#define MICO_UNUSED 0xFF
typedef enum
{
MICO_SYS_LED,
MICO_RF_LED,
BOOT_SEL,
MFG_SEL,
EasyLink_BUTTON,
MICO_GPIO_1 ,
MICO_GPIO_2,
//MICO_GPIO_3,
MICO_GPIO_4,
MICO_GPIO_5,
MICO_GPIO_6,
MICO_GPIO_7,
MICO_GPIO_8,
MICO_GPIO_9,
MICO_GPIO_10,
//MICO_GPIO_11,
MICO_GPIO_12,
MICO_GPIO_13,
MICO_GPIO_14,
//MICO_GPIO_15,
//MICO_GPIO_16,
//MICO_GPIO_17,
MICO_GPIO_18,
MICO_GPIO_19,
MICO_GPIO_20,
MICO_GPIO_21,
MICO_GPIO_22,
MICO_GPIO_23,
//MICO_GPIO_24,
//MICO_GPIO_25,
//MICO_GPIO_26,
//MICO_GPIO_27,
//MICO_GPIO_28,
MICO_GPIO_29,
//MICO_GPIO_30,
MICO_GPIO_MAX, /* Denotes the total number of GPIO port aliases. Not a valid GPIO alias */
MICO_GPIO_NONE,
} mico_gpio_t;
typedef enum
{
MICO_SPI_1,
MICO_SPI_2,
MICO_SPI_3,
MICO_SPI_MAX, /* Denotes the total number of SPI port aliases. Not a valid SPI alias */
MICO_SPI_NONE,
} mico_spi_t;
typedef enum
{
MICO_I2C_1,
MICO_I2C_2,
MICO_I2C_MAX, /* Denotes the total number of I2C port aliases. Not a valid I2C alias */
MICO_I2C_NONE,
} mico_i2c_t;
typedef enum
{
MICO_PWM_1,
MICO_PWM_2,
MICO_PWM_3,
MICO_PWM_4,
MICO_PWM_MAX, /* Denotes the total number of PWM port aliases. Not a valid PWM alias */
MICO_PWM_NONE,
} mico_pwm_t;
typedef enum
{
MICO_ADC_1,
MICO_ADC_2,
MICO_ADC_3,
MICO_ADC_MAX, /* Denotes the total number of ADC port aliases. Not a valid ADC alias */
MICO_ADC_NONE,
} mico_adc_t;
typedef enum
{
MICO_UART_1,
MICO_UART_2,
MICO_UART_MAX, /* Denotes the total number of UART port aliases. Not a valid UART alias */
MICO_UART_NONE,
} mico_uart_t;
typedef enum
{
MICO_FLASH_EMBEDDED,
MICO_FLASH_SPI,
MICO_FLASH_MAX,
MICO_FLASH_NONE,
} mico_flash_t;
typedef enum
{
MICO_PARTITION_USER_MAX
} mico_user_partition_t;
#ifdef BOOTLOADER
#define STDIO_UART MICO_UART_NONE
#define STDIO_UART_BAUDRATE (115200)
#else
#define STDIO_UART MICO_UART_NONE
#define STDIO_UART_BAUDRATE (115200)
#endif
#define UART_FOR_APP MICO_UART_1
#define MFG_TEST MICO_UART_1
#define CLI_UART MICO_UART_1
/* Components connected to external I/Os*/
#define Standby_SEL (MICO_GPIO_29)
/* I/O connection <-> Peripheral Connections */
#define MICO_I2C_CP (MICO_I2C_1)
//#define USE_MICO_SPI_FLASH
#define MICO_FLASH_FOR_PARA MICO_FLASH_SPI
#define PARA_START_ADDRESS (uint32_t)0x00000020
#define PARA_END_ADDRESS (uint32_t)0x00003FFF
#define PARA_FLASH_SIZE (PARA_END_ADDRESS - PARA_START_ADDRESS + 1) /* 4k bytes*/
#ifdef __cplusplus
} /*extern "C" */
#endif

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 1
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 1000
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#endif /* CONFIG_H */

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47
Living_SDK/board/asr5501/Config.in Normal file
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config AOS_BOARD_ASR5501
bool "ASR5501"
select AOS_MCU_ASR5501
select AOS_COMP_KERNEL_INIT
select AOS_COMP_LWIP if AOS_NETWORK_SAL
select AOS_COMP_NETMGR
help
if AOS_BOARD_ASR5501
# Configurations for board asr5501
config DEBUG_CONFIG_PANIC
bool "Enable debug panic feature"
default y
help
set to y if you want to enable panic debug feature when system crash happened,
default y
config DEBUG_CONFIG_BACKTRACE
bool "Enable stack backtrace feature"
default y
help
set to y if you want to enable stack backtrace feature when system crash happened,
default y
# "BSP SUPPORT FEATURE"
config BSP_SUPPORT_UART
bool
default y
config BSP_SUPPORT_GPIO
bool
default y
config BSP_SUPPORT_FLASH
bool
default y
config BSP_SUPPORT_I2C
bool
default y
config BSP_SUPPORT_WIFI
bool
default y
endif

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## Overview
This is a board demo for consulting, not a true realization.
## Feature of Board
## Directories
```sh
aaboard_demo # configuration files for board aaboard_demo
=============================================================================================================
Dir\File Description Necessary for kernel run
=============================================================================================================
|-- drivers # board peripheral driver N
|-- config
| |-- board.h # board config file, define for user, such as uart port num Y
| |-- k_config.c # user's kernel hook and mm memory region define Y
| |-- k_config.h # kernel config file .h Y
| |-- partition_conf.c # board flash config file N
|-- startup
| |-- board.c # board_init implement Y
| |-- startup.c # main entry file Y
| |-- startup_gcc.s # board startup assember for gcc Y
| |-- startup_iar.s # board startup assember for iar Y
| |-- startup_keil.s # board startup assember for keil Y
|-- aaboard_demo.icf # linkscript file for iar Y
|-- aaboard_demo.ld # linkscript file for gcc Y
|-- aaboard_demo.sct # linkscript file for sct Y
|-- aos.mk # board makefile Y
|-- Config.in # menuconfig component config Y
|-- ucube.py # config for CI autorun app N
```
## Board Hardware Resources
## Pin Mapping
## Driver Support
## Programming
## Debugging
## Update log
## Reference

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Living_SDK/board/asr5501/asr5501.mk Executable file
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NAME := board_asr5501
MODULE := ASR5501
HOST_ARCH := Cortex-M4
HOST_MCU_FAMILY := asr5501
SUPPORT_BINS := no
define get-os-version
"AOS-R"-$(CURRENT_TIME)
endef
CONFIG_SYSINFO_OS_VERSION := $(call get-os-version)
$(NAME)_SOURCES := config/partition_conf.c \
config/k_config.c \
startup/startup.c \
startup/startup_cm4.S \
startup/board.c
GLOBAL_INCLUDES += . \
./config \
./drivers/include \
./drivers/include/lwip_if \
$(NAME)_CFLAGS += -DLEGA_CM4 -DALIOS_SUPPORT -DWIFI_DEVICE -D_SPI_FLASH_ENABLE_ -DDCDC_PFMMODE_CLOSE -DCFG_MIMO_UF
$(NAME)_CFLAGS += -DCFG_BATX=1 -DCFG_BARX=1 -DCFG_REORD_BUF=4 -DCFG_SPC=4 -DCFG_TXDESC0=4 -DCFG_TXDESC1=4 -DCFG_TXDESC2=4 -DCFG_TXDESC3=4 -DCFG_TXDESC4=4 -DCFG_CMON -DCFG_MDM_VER_V21 -DCFG_SOFTAP_SUPPORT -DCFG_SNIFFER_SUPPORT -DCFG_DBG=2 -D__FPU_PRESENT=1 -DDX_CC_TEE -DHASH_SHA_512_SUPPORTED -DCC_HW_VERSION=0xF0 -DDLLI_MAX_BUFF_SIZE=0x10000 -DSSI_CONFIG_TRNG_MODE=0
#default a0v2 config
ifeq ($(buildsoc),a0v1)
$(NAME)_CFLAGS += -DLEGA_A0V1
GLOBAL_LDS_FILES += $(SOURCE_ROOT)/board/asr5501/gcc.ld
else
$(NAME)_CFLAGS += -DLEGA_A0V2
GLOBAL_LDS_FILES += $(SOURCE_ROOT)/board/asr5501/gcc_a0v2.ld
endif
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_LEGAWIFI
CONFIG_SYSINFO_DEVICE_NAME := 5501A0V240A
GLOBAL_DEFINES += STDIO_UART=1
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
GLOBAL_CFLAGS += -DLEGA_CM4
GLOBAL_CFLAGS += -DAWSS_REGISTRAR_LOWPOWER_EN
EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_ota_bin.mk
#GLOBAL_DEFINES += CONFIG_SOCKET_ACCESS_CONTROL
GLOBAL_CFLAGS += -DCONFIG_TCP_SOCKET_ACCESS_CONTROL

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#ifndef __BOARD_H__
#define __BOARD_H__
#include "hal/hal.h"
extern hal_logic_partition_t hal_partitions[];
extern void flash_partition_init(void);
typedef enum {
PORT_UART_STD,
PORT_UART_AT,
PORT_UART_RS485,
PORT_UART_SCANNER,
PORT_UART_LORA,
PORT_UART_TEMP,
PORT_UART_SIZE,
PORT_UART_INVALID = 255
}PORT_UART_TYPE;
#endif //__BOARD_H__

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <k_api.h>
#include <assert.h>
#include <stdio.h>
#include <sys/time.h>
#if (RHINO_CONFIG_HW_COUNT > 0)
void soc_hw_timer_init(void)
{
}
hr_timer_t soc_hr_hw_cnt_get(void)
{
return 0;
//return *(volatile uint64_t *)0xc0000120;
}
lr_timer_t soc_lr_hw_cnt_get(void)
{
return 0;
}
#endif /* RHINO_CONFIG_HW_COUNT */
#if (RHINO_CONFIG_INTRPT_GUARD > 0)
void soc_intrpt_guard(void)
{
}
#endif
#if (RHINO_CONFIG_INTRPT_STACK_REMAIN_GET > 0)
size_t soc_intrpt_stack_remain_get(void)
{
return 0;
}
#endif
#if (RHINO_CONFIG_INTRPT_STACK_OVF_CHECK > 0)
void soc_intrpt_stack_ovf_check(void)
{
}
#endif
#if (RHINO_CONFIG_MM_TLF > 0)
#if defined (__CC_ARM) /* Keil / armcc */
#define HEAP_BUFFER_SIZE 1024*120
uint8_t g_heap_buf[HEAP_BUFFER_SIZE];
k_mm_region_t g_mm_region[] = {{g_heap_buf, HEAP_BUFFER_SIZE}};
#elif defined (__ICCARM__)/* IAR */
#define HEAP_BUFFER_SIZE 1024*120
uint8_t g_heap_buf[HEAP_BUFFER_SIZE];
k_mm_region_t g_mm_region[] = {{g_heap_buf, HEAP_BUFFER_SIZE}};
#else /* GCC */
extern void *heap_start;
extern void *heap_end;
extern void *heap_len;
/* heap_start and heap_len is set by linkscript(*.ld) */
k_mm_region_t g_mm_region[] = {{(uint8_t*)&heap_start,(size_t)&heap_len}};
#endif
int g_region_num = sizeof(g_mm_region)/sizeof(k_mm_region_t);
#endif
#if (RHINO_CONFIG_MM_LEAKCHECK > 0 )
extern int __bss_start__, __bss_end__, _sdata, _edata;
void aos_mm_leak_region_init(void)
{
#if (RHINO_CONFIG_MM_DEBUG > 0)
krhino_mm_leak_region_init(&__bss_start__, &__bss_end__);
krhino_mm_leak_region_init(&_sdata, &_edata);
#endif
}
#endif
#if (RHINO_CONFIG_TASK_STACK_CUR_CHECK > 0)
size_t soc_get_cur_sp()
{
size_t sp = 0;
#if defined (__GNUC__)&&!defined(__CC_ARM)
asm volatile(
"mov %0,sp\n"
:"=r"(sp));
#endif
return sp;
}
static void soc_print_stack()
{
void *cur, *end, *start;
int stack_size;
int i=0;
int *p;
ktask_t * cur_task;
cur_task = krhino_cur_task_get();
start = cur_task->task_stack_base;
stack_size = cur_task->stack_size;
end = start + stack_size*4;
cur = (void *)soc_get_cur_sp();
p = (int*)cur;
while(p < (int*)end) {
if(i%4==0) {
printf("\r\n%08lx:",(uint32_t)p);
}
printf("%08x ", *p);
i++;
p++;
}
printf("=============,task_name:%s,start:%x,stack:%x,cur:%x\r\n", cur_task->task_name, (unsigned int)start, stack_size, (unsigned int)cur);
return;
}
#endif
void soc_err_proc(kstat_t err)
{
(void)err;
#if (RHINO_CONFIG_TASK_STACK_CUR_CHECK > 0)
soc_print_stack();
#endif
assert(0);
}
#if (RHINO_CONFIG_USER_HOOK > 0)
/**
* This function will provide init hook
*/
void krhino_init_hook(void)
{
return;
}
/**
* This function will provide system start hook
*/
void krhino_start_hook(void)
{
return;
}
/**
* This function will provide task create hook
* @param[in] task pointer to the task
*/
void krhino_task_create_hook(ktask_t *task)
{
return;
}
/**
* This function will provide task delete hook
* @param[in] task pointer to the task
*/
void krhino_task_del_hook(ktask_t *task, res_free_t *arg)
{
return;
}
/**
* This function will provide task abort hook
* @param[in] task pointer to the task
*/
void krhino_task_abort_hook(ktask_t *task)
{
return;
}
/**
* This function will provide task switch hook
*/
void krhino_task_switch_hook(ktask_t *orgin, ktask_t *dest)
{
return;
}
/**
* This function will provide system tick hook
*/
void krhino_tick_hook(void)
{
return;
}
/**
* This function will provide idle pre hook
*/
void krhino_idle_pre_hook(void)
{
return;
}
/**
* This function will provide idle hook
*/
void krhino_idle_hook(void)
{
extern void pmu_idle_hook(void);
pmu_idle_hook();
}
/**
* This function will provide krhino_mm_alloc hook
*/
void krhino_mm_alloc_hook(void *mem, size_t size)
{
return;
}
#endif
#if (RHINO_CONFIG_TRACE == 0)
void trace_start(void)
{
printf("trace config close!!!\r\n");
}
#endif
krhino_err_proc_t g_err_proc = soc_err_proc;

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef K_CONFIG_H
#define K_CONFIG_H
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 0
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 0
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 0
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 1000
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 512
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 128
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* lowpower conf */
#ifndef WIFI_CONFIG_SUPPORT_LOWPOWER
#define WIFI_CONFIG_SUPPORT_LOWPOWER 0
#endif
#ifndef WIFI_CONFIG_LISTENSET_BINIT
#define WIFI_CONFIG_LISTENSET_BINIT 0
#endif
#ifndef WIFI_CONFIG_LISTEN_INTERVAL
#define WIFI_CONFIG_LISTEN_INTERVAL 1
#endif
#ifndef WIFI_CONFIG_RECEIVE_DTIM
#define WIFI_CONFIG_RECEIVE_DTIM 1
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#endif /* K_CONFIG_H */

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Living_SDK/board/asr5501/config/partition_conf.c Normal file
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#include <aos/aos.h>
#include "hal/soc/soc.h"
#include "lega_flash.h"
/* Logic partition on flash devices */
hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX];
extern const lega_logic_partition_t lega_partitions[];
void flash_partition_init(void)
{
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_owner = lega_partitions[PARTITION_BOOTLOADER].partition_owner;
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_description = lega_partitions[PARTITION_BOOTLOADER].partition_description;
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_start_addr = lega_partitions[PARTITION_BOOTLOADER].partition_start_addr;
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_length = lega_partitions[PARTITION_BOOTLOADER].partition_length;
hal_partitions[HAL_PARTITION_BOOTLOADER].partition_options = lega_partitions[PARTITION_BOOTLOADER].partition_options ;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = lega_partitions[PARTITION_PARAMETER_1].partition_owner;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = lega_partitions[PARTITION_PARAMETER_1].partition_description;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = lega_partitions[PARTITION_PARAMETER_1].partition_start_addr;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = lega_partitions[PARTITION_PARAMETER_1].partition_length;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = lega_partitions[PARTITION_PARAMETER_1].partition_options ;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = lega_partitions[PARTITION_PARAMETER_2].partition_owner ;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = lega_partitions[PARTITION_PARAMETER_2].partition_description;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = lega_partitions[PARTITION_PARAMETER_2].partition_start_addr;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = lega_partitions[PARTITION_PARAMETER_2].partition_length;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = lega_partitions[PARTITION_PARAMETER_2].partition_options;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_owner = lega_partitions[PARTITION_PARAMETER_3].partition_owner ;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_description = lega_partitions[PARTITION_PARAMETER_3].partition_description;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_start_addr = lega_partitions[PARTITION_PARAMETER_3].partition_start_addr;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_length = lega_partitions[PARTITION_PARAMETER_3].partition_length;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_options = lega_partitions[PARTITION_PARAMETER_3].partition_options;
hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = lega_partitions[PARTITION_APPLICATION].partition_owner;
hal_partitions[HAL_PARTITION_APPLICATION].partition_description = lega_partitions[PARTITION_APPLICATION].partition_description;
hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = lega_partitions[PARTITION_APPLICATION].partition_start_addr;
hal_partitions[HAL_PARTITION_APPLICATION].partition_length = lega_partitions[PARTITION_APPLICATION].partition_length;
hal_partitions[HAL_PARTITION_APPLICATION].partition_options = lega_partitions[PARTITION_APPLICATION].partition_options;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_owner = lega_partitions[PARTITION_OTA_TEMP].partition_owner;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_description = lega_partitions[PARTITION_OTA_TEMP].partition_description;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_start_addr = lega_partitions[PARTITION_OTA_TEMP].partition_start_addr;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_length = lega_partitions[PARTITION_OTA_TEMP].partition_length;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_options = lega_partitions[PARTITION_OTA_TEMP].partition_options;
}

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Living_SDK/board/asr5501/config/ram.ini Normal file
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FUNC void Setup (void) {
SP = _RDWORD(0x10040000); // Setup Stack Pointer
PC = _RDWORD(0x10040004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x10040000); // Setup Vector Table Offset Register
}
load ./Objects/linkkitapp@asr5501.elf incremental
Setup(); // Setup for Running
g, main

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Living_SDK/board/asr5501/drivers/include/lega_rhino.h Normal file
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/*
* Copyright (C) 2015-2018 ASR Group Holding Limited
*/
#ifndef __LEGARTOS_H__
#define __LEGARTOS_H__
#include <k_api.h>
#include <ctype.h>
#include "port.h"
#define LEGA_NEVER_TIMEOUT (0xFFFFFFFF)
#define LEGA_WAIT_FOREVER (0xFFFFFFFF)
#define LEGA_NO_WAIT (0)
typedef enum
{
kNoErr=0,
kGeneralErr,
kTimeoutErr,
}OSStatus;
typedef enum
{
FALSE=0,
TRUE=1,
}OSBool;
typedef void * lega_semaphore_t;
typedef void * lega_mutex_t;
typedef void * lega_thread_t;
typedef void * lega_queue_t;
//typedef void * lega_event_t;// LEGA OS event: lega_semaphore_t, lega_mutex_t or lega_queue_t
typedef void (*timer_handler_t)( void* arg );
//typedef OSStatus (*event_handler_t)( void* arg );
typedef struct
{
void * handle;
timer_handler_t function;
void * arg;
}lega_timer_t;
typedef uint32_t lega_thread_arg_t;
typedef void (*lega_thread_function_t)( lega_thread_arg_t arg );
/** @defgroup LEGA_RTOS_Thread LEGA RTOS Thread Management Functions
* @brief Provide thread creation, delete, suspend, resume, and other RTOS management API
* @verbatim
* LEGA thread priority table
*
* +----------+-----------------+
* | Priority | Thread |
* |----------|-----------------|
* | 0 | LEGA | Highest priority
* | 1 | Network |
* | 2 | |
* | 3 | Network worker |
* | 4 | |
* | 5 | Default Library |
* | | Default worker |
* | 6 | |
* | 7 | Application |
* | 8 | |
* | 9 | Idle | Lowest priority
* +----------+-----------------+
* @endverbatim
* @{
*/
OSBool lega_rtos_is_in_interrupt_context(void);
/** @brief Creates and starts a new thread
*
* @param thread : Pointer to variable that will receive the thread handle (can be null)
* @param priority : A priority number.
* @param name : a text name for the thread (can be null)
* @param function : the main thread function
* @param stack_size : stack size for this thread
* @param arg : argument which will be passed to thread function
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_create_thread( lega_thread_t* thread, uint8_t priority, const char* name, lega_thread_function_t function, uint32_t stack_size, lega_thread_arg_t arg );
/** @brief Deletes a terminated thread
*
* @param thread : the handle of the thread to delete, , NULL is the current thread
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_delete_thread( lega_thread_t* thread );
/** @defgroup LEGA_RTOS_SEM LEGA RTOS Semaphore Functions
* @brief Provide management APIs for semaphore such as init,set,get and dinit.
* @{
*/
/** @brief Initialises a counting semaphore and set count to 0
*
* @param semaphore : a pointer to the semaphore handle to be initialised
* @param count : the max count number of this semaphore
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_init_semaphore( lega_semaphore_t* semaphore, int count );
/** @brief Set (post/put/increment) a semaphore
*
* @param semaphore : a pointer to the semaphore handle to be set
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_set_semaphore( lega_semaphore_t* semaphore );
/** @brief Get (wait/decrement) a semaphore
*
* @Details Attempts to get (wait/decrement) a semaphore. If semaphore is at zero already,
* then the calling thread will be suspended until another thread sets the
* semaphore with @ref lega_rtos_set_semaphore
*
* @param semaphore : a pointer to the semaphore handle
* @param timeout_ms: the number of milliseconds to wait before returning
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_get_semaphore( lega_semaphore_t* semaphore, uint32_t timeout_ms );
/** @brief De-initialise a semaphore
*
* @Details Deletes a semaphore created with @ref lega_rtos_init_semaphore
*
* @param semaphore : a pointer to the semaphore handle
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deinit_semaphore( lega_semaphore_t* semaphore );
/**
* @}
*/
#define lega_rtos_declare_critical() CPSR_ALLOC()
/** @brief Enter a critical session, all interrupts are disabled
*
* @return none
*/
#define lega_rtos_enter_critical() RHINO_CRITICAL_ENTER()
//void lega_rtos_enter_critical( void );
/** @brief Exit a critical session, all interrupts are enabled
*
* @return none
*/
#define lega_rtos_exit_critical() RHINO_CRITICAL_EXIT()
//void lega_rtos_exit_critical( void );
/** @defgroup LEGA_RTOS_MUTEX LEGA RTOS Mutex Functions
* @brief Provide management APIs for Mutex such as init,lock,unlock and dinit.
* @{
*/
/** @brief Initialises a mutex
*
* @Details A mutex is different to a semaphore in that a thread that already holds
* the lock on the mutex can request the lock again (nested) without causing
* it to be suspended.
*
* @param mutex : a pointer to the mutex handle to be initialised
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_init_mutex( lega_mutex_t* mutex );
/** @brief Obtains the lock on a mutex
*
* @Details Attempts to obtain the lock on a mutex. If the lock is already held
* by another thead, the calling thread will be suspended until the mutex
* lock is released by the other thread.
*
* @param mutex : a pointer to the mutex handle to be locked
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_lock_mutex( lega_mutex_t* mutex, uint32_t timeout_ms );
/** @brief Releases the lock on a mutex
*
* @Details Releases a currently held lock on a mutex. If another thread
* is waiting on the mutex lock, then it will be resumed.
*
* @param mutex : a pointer to the mutex handle to be unlocked
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_unlock_mutex( lega_mutex_t* mutex );
/** @brief De-initialise a mutex
*
* @Details Deletes a mutex created with @ref lega_rtos_init_mutex
*
* @param mutex : a pointer to the mutex handle
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deinit_mutex( lega_mutex_t* mutex );
/**
* @}
*/
/** @defgroup LEGA_RTOS_QUEUE LEGA RTOS FIFO Queue Functions
* @brief Provide management APIs for FIFO such as init,push,pop and dinit.
* @{
*/
/** @brief Initialises a FIFO queue
*
* @param queue : a pointer to the queue handle to be initialised
* @param name : a text string name for the queue (NULL is allowed)
* @param message_size : size in bytes of objects that will be held in the queue
* @param number_of_messages : depth of the queue - i.e. max number of objects in the queue
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_init_queue( lega_queue_t* queue, const char* name, uint32_t message_size, uint32_t number_of_messages );
/** @brief Pushes an object onto a queue
*
* @param queue : a pointer to the queue handle
* @param message : the object to be added to the queue. Size is assumed to be
* the size specified in @ref lega_rtos_init_queue
* @param timeout_ms: the number of milliseconds to wait before returning
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error or timeout occurred
*/
OSStatus lega_rtos_push_to_queue( lega_queue_t* queue, void* message, uint32_t timeout_ms );
/** @brief Pops an object off a queue
*
* @param queue : a pointer to the queue handle
* @param message : pointer to a buffer that will receive the object being
* popped off the queue. Size is assumed to be
* the size specified in @ref lega_rtos_init_queue , hence
* you must ensure the buffer is long enough or memory
* corruption will result
* @param timeout_ms: the number of milliseconds to wait before returning
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error or timeout occurred
*/
OSStatus lega_rtos_pop_from_queue( lega_queue_t* queue, void* message, uint32_t timeout_ms );
/** @brief De-initialise a queue created with @ref lega_rtos_init_queue
*
* @param queue : a pointer to the queue handle
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deinit_queue( lega_queue_t* queue );
/** @brief Check if a queue is empty
*
* @param queue : a pointer to the queue handle
*
* @return true : queue is empty.
* @return false : queue is not empty.
*/
OSBool lega_rtos_is_queue_empty( lega_queue_t* queue );
/** @brief Check if a queue is full
*
* @param queue : a pointer to the queue handle
*
* @return true : queue is empty.
* @return false : queue is not empty.
*/
OSBool lega_rtos_is_queue_full( lega_queue_t* queue );
/**
* @}
*/
/** @defgroup LEGA_RTOS_TIMER LEGA RTOS Timer Functions
* @brief Provide management APIs for timer such as init,start,stop,reload and dinit.
* @{
*/
/**
* @brief Initialize a RTOS timer
*
* @note Timer does not start running until @ref lega_start_timer is called
*
* @param timer : a pointer to the timer handle to be initialised
* @param time_ms : Timer period in milliseconds
* @param function : the callback handler function that is called each time the
* timer expires
* @param arg : an argument that will be passed to the callback function
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_init_timer( lega_timer_t* timer, uint32_t time_ms, timer_handler_t function, void* arg );
/** @brief Starts a RTOS timer running
*
* @note Timer must have been previously initialised with @ref lega_rtos_init_timer
*
* @param timer : a pointer to the timer handle to start
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_start_timer( lega_timer_t* timer );
/** @brief Stops a running RTOS timer
*
* @note Timer must have been previously started with @ref lega_rtos_init_timer
*
* @param timer : a pointer to the timer handle to stop
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_stop_timer( lega_timer_t* timer );
/** @brief Reloads a RTOS timer that has expired
*
* @note This is usually called in the timer callback handler, to
* reschedule the timer for the next period.
*
* @param timer : a pointer to the timer handle to reload
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_reload_timer( lega_timer_t* timer );
/** @brief De-initialise a RTOS timer
*
* @note Deletes a RTOS timer created with @ref lega_rtos_init_timer
*
* @param timer : a pointer to the RTOS timer handle
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deinit_timer( lega_timer_t* timer );
/** @brief Check if an RTOS timer is running
*
* @param timer : a pointer to the RTOS timer handle
*
* @return true : if running.
* @return false : if not running
*/
OSBool lega_rtos_is_timer_running( lega_timer_t* timer );
/**
* @brief Gets time in miiliseconds since RTOS start
*
* @note: Since this is only 32 bits, it will roll over every 49 days, 17 hours.
*
* @returns Time in milliseconds since RTOS started.
*/
uint32_t lega_rtos_get_time(void);
/**
* @}
*/
/** @brief Suspend current thread for a specific time
*
* @param num_ms : A time interval (Unit: millisecond)
*
* @return kNoErr.
*/
OSStatus lega_rtos_delay_milliseconds( uint32_t num_ms );
#define lega_rtos_malloc(s) _lega_rtos_malloc(s,__FUNCTION__,__LINE__)
void *_lega_rtos_malloc(uint32_t xWantedSize,const char * function,uint32_t line);
void lega_rtos_free(void *mem);
void lega_system_reset();
#if 0
/** @brief Creates a worker thread
*
* Creates a worker thread
* A worker thread is a thread in whose context timed and asynchronous events
* execute.
*
* @param worker_thread : a pointer to the worker thread to be created
* @param priority : thread priority
* @param stack_size : thread's stack size in number of bytes
* @param event_queue_size : number of events can be pushed into the queue
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_create_worker_thread( lega_worker_thread_t* worker_thread, uint8_t priority, uint32_t stack_size, uint32_t event_queue_size );
/** @brief Deletes a worker thread
*
* @param worker_thread : a pointer to the worker thread to be created
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_delete_worker_thread( lega_worker_thread_t* worker_thread );
/** @brief Suspend a thread
*
* @param thread : the handle of the thread to suspend, NULL is the current thread
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
void lega_rtos_suspend_thread(lega_thread_t* thread);
/** @brief Suspend all other thread
*
* @param none
*
* @return none
*/
void lega_rtos_suspend_all_thread(void);
/** @brief Rresume all other thread
*
* @param none
*
* @return none
*/
long lega_rtos_resume_all_thread(void);
/** @brief Sleeps until another thread has terminated
*
* @Details Causes the current thread to sleep until the specified other thread
* has terminated. If the processor is heavily loaded with higher priority
* tasks, this thread may not wake until significantly after the thread termination.
*
* @param thread : the handle of the other thread which will terminate
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_thread_join( lega_thread_t* thread );
/** @brief Forcibly wakes another thread
*
* @Details Causes the specified thread to wake from suspension. This will usually
* cause an error or timeout in that thread, since the task it was waiting on
* is not complete.
*
* @param thread : the handle of the other thread which will be woken
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_thread_force_awake( lega_thread_t* thread );
/** @brief Checks if a thread is the current thread
*
* @Details Checks if a specified thread is the currently running thread
*
* @param thread : the handle of the other thread against which the current thread
* will be compared
*
* @return true : specified thread is the current thread
* @return false : specified thread is not currently running
*/
OSBool lega_rtos_is_current_thread( lega_thread_t* thread );
/** @brief Print Thread status into buffer
*
* @param buffer, point to buffer to store thread status
* @param length, length of the buffer
*
* @return none
*/
OSStatus lega_rtos_print_thread_status( char* buffer, int length );
/**
* @}
*/
/** @defgroup LEGA_RTOS_EVENT LEGA RTOS Event Functions
* @{
*/
/**
* @brief Sends an asynchronous event to the associated worker thread
*
* @param worker_thread :the worker thread in which context the callback should execute from
* @param function : the callback function to be called from the worker thread
* @param arg : the argument to be passed to the callback function
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_send_asynchronous_event( lega_worker_thread_t* worker_thread, event_handler_t function, void* arg );
/** Requests a function be called at a regular interval
*
* This function registers a function that will be called at a regular
* interval. Since this is based on the RTOS time-slice scheduling, the
* accuracy is not high, and is affected by processor load.
*
* @param event_object : pointer to a event handle which will be initialised
* @param worker_thread : pointer to the worker thread in whose context the
* callback function runs on
* @param function : the callback function that is to be called regularly
* @param time_ms : the time period between function calls in milliseconds
* @param arg : an argument that will be supplied to the function when
* it is called
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_register_timed_event( lega_timed_event_t* event_object, lega_worker_thread_t* worker_thread, event_handler_t function, uint32_t time_ms, void* arg );
/** Removes a request for a regular function execution
*
* This function de-registers a function that has previously been set-up
* with @ref lega_rtos_register_timed_event.
*
* @param event_object : the event handle used with @ref lega_rtos_register_timed_event
*
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deregister_timed_event( lega_timed_event_t* event_object );
/**
* @}
*/
int SetTimer(unsigned long ms, void (*psysTimerHandler)(void));
int SetTimer_uniq(unsigned long ms, void (*psysTimerHandler)(void));
int UnSetTimer(void (*psysTimerHandler)(void));
/** @brief Initialize an endpoint for a RTOS event, a file descriptor
* will be created, can be used for select
*
* @param event_handle : lega_semaphore_t, lega_mutex_t or lega_queue_t
*
* @retval On success, a file descriptor for RTOS event is returned.
* On error, -1 is returned.
*/
int lega_rtos_init_event_fd(lega_event_t event_handle);
/** @brief De-initialise an endpoint created from a RTOS event
*
* @param fd : file descriptor for RTOS event
*
* @retval 0 for success. On error, -1 is returned.
*/
int lega_rtos_deinit_event_fd(int fd);
/**
* @}
*/
#endif
#endif //__LEGARTOS_H__

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/**
****************************************************************************************
*
* @file lega_wifi_api.h
*
* @brief WiFi API.
*
* Copyright (C) ASR
*
****************************************************************************************
*/
#ifndef _LEGA_WIFI_API_H_
#define _LEGA_WIFI_API_H_
#include <stdint.h>
#include "lega_cm4.h"
/**
* @brief wlan network interface enumeration definition.
*/
typedef enum {
SOFTAP, /*Act as an access point, and other station can connect, 4 stations Max*/
STA, /*Act as a station which can connect to an access point*/
} lega_wlan_type_e;
enum {
WLAN_DHCP_DISABLE = 0,
WLAN_DHCP_CLIENT,
WLAN_DHCP_SERVER,
};
typedef enum {
EVENT_STATION_UP = 1, /*used in station mode,
indicate station associated in open mode or 4-way-handshake done in WPA/WPA2*/
EVENT_STATION_DOWN, /*used in station mode, indicate station deauthed*/
EVENT_AP_UP, /*used in softap mode, indicate softap enabled*/
EVENT_AP_DOWN, /*used in softap mode, indicate softap disabled*/
} lega_wifi_event_e;
typedef enum {
CONNECT_SUCC,
CONNECT_SCAN_FAIL,
CONNECT_CONN_FAIL,
} lega_start_adv_results_e;
/**
* @brief Scan result using normal scan.
*/
typedef struct {
uint8_t is_scan_adv;
char ap_num; /**< The number of access points found in scanning. */
struct {
char ssid[32+1]; /*ssid max len:32. +1 is for '\0'. when ssidlen is 32 */
char ap_power; /**< Signal strength, min:0, max:100. */
char bssid[6]; /* The BSSID of an access point. */
char channel; /* The RF frequency, 1-13 */
uint8_t security; /* Security type, @ref wlan_sec_type_t */
} * ap_list;
} lega_wlan_scan_result_t;
typedef enum {
WLAN_SECURITY_OPEN, //NONE
WLAN_SECURITY_WEP, //WEP
WLAN_SECURITY_WPA, //WPA
WLAN_SECURITY_WPA2, //WPA2
WLAN_SECURITY_AUTO, //WPA or WPA2
WLAN_SECURITY_MAX,
} lega_wlan_security_e;
/*used in event callback of station mode, indicate softap informatino which is connected*/
typedef struct {
int rssi; /* rssi */
char ssid[32+1]; /* ssid max len:32. +1 is for '\0' when ssidlen is 32 */
char pwd[64+1]; /* pwd max len:64. +1 is for '\0' when pwdlen is 64 */
char bssid[6]; /* BSSID of the wlan needs to be connected.*/
char ssid_len; /*ssid length*/
char pwd_len; /*password length*/
char channel; /* wifi channel 0-13.*/
char security; /*refer to lega_wlan_security_e*/
} lega_wlan_ap_info_adv_t;
/*only used in station mode*/
typedef struct {
char dhcp; /* no use currently */
char macaddr[16]; /* mac address on the target wlan interface, ASCII*/
char ip[16]; /* Local IP address on the target wlan interface, ASCII*/
char gate[16]; /* Router IP address on the target wlan interface, ASCII */
char mask[16]; /* Netmask on the target wlan interface, ASCII*/
char dns[16]; /* no use currently , ASCII*/
char broadcastip[16]; /* no use currently , ASCII*/
} lega_wlan_ip_stat_t;
/*only used in station mode*/
typedef struct {
int is_connected; /* The link to wlan is established or not, 0: disconnected, 1: connected. */
int wifi_strength; /* Signal strength of the current connected AP */
char ssid[32+1]; /* ssid max len:32. +1 is for '\0'. when ssidlen is 32 */
char bssid[6]; /* BSSID of the current connected wlan */
int channel; /* Channel of the current connected wlan */
} lega_wlan_link_stat_t;
/*used in open cmd of hal_wifi_module_t*/
typedef struct {
char wifi_mode; /* refer to hal_wifi_type_t*/
char security; /* security mode */
char wifi_ssid[32]; /* in station mode, indicate SSID of the wlan needs to be connected.
in softap mode, indicate softap SSID*/
char wifi_key[64]; /* in station mode, indicate Security key of the wlan needs to be connected,
in softap mode, indicate softap password.(ignored in an open system.) */
char local_ip_addr[16]; /* used in softap mode to config ip for dut */
char net_mask[16]; /* used in softap mode to config gateway for dut */
char gateway_ip_addr[16]; /* used in softap mode to config netmask for dut */
char dns_server_ip_addr[16]; /* no use currently */
char dhcp_mode; /* no use currently */
char channel; /* softap channel in softap mode; connect channel in sta mode*/
char mac_addr[6]; /* connect bssid in sta mode*/
char reserved[32]; /* no use currently */
int wifi_retry_interval; /* no use currently */
int interval; /* used in softap mode to config beacon listen interval */
int hide; /* used in softap mode to config hidden SSID */
} lega_wlan_init_type_t;
/** @brief wifi init functin, user should call it before use any wifi cmd
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_init(void);
/** @brief wifi deinit functin, call it when donot use wifi any more to free resources
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_deinit(void);
/** @brief used in station and softap mode, open wifi cmd
*
* @param init_info : refer to lega_wlan_init_type_t
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_open(lega_wlan_init_type_t* init_info);
/** @brief used in station and softap mode, close wifi cmd
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_close(void);
/** @brief used in station mode, scan cmd
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_start_scan(void);
/** @brief used in station mode, scan cmd
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_start_scan_adv(void);
/** @brief used in station mode, scan cmd
*
* @param ssid : target ssid to scan
* @param is_scan_advance :scan to get bssid, channel and security
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_start_scan_active(const char *ssid, uint8_t is_scan_advance);
/** @brief used in station and softap mode, get mac address(in hex mode) of WIFI device
*
* @param mac_addr : pointer to get the mac address
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_get_mac_address(uint8_t *mac_addr);
/** @brief used in station and softap mode, set mac address for WIFI device
*
* @param mac_addr : src mac address pointer to set
*
*/
void lega_wlan_set_mac_address(uint8_t *mac_addr);
/** @brief used in station mode, get the ip information
*
* @param void
* @return NULL : error occurred.
* @return pointer : ip status got.
*/
lega_wlan_ip_stat_t * lega_wlan_get_ip_status(void);
/** @brief used in station mode, get link status information
*
* @param link_status : refer to lega_wlan_link_stat_t
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_get_link_status(lega_wlan_link_stat_t *link_status);
/** @brief used in station mode, get the associated ap information
*
* @param void
* @return NULL : error occurred.
* @return pointer : associated ap info got.
*/
lega_wlan_ap_info_adv_t *lega_wlan_get_associated_apinfo(void);
/*used in sniffer mode, open sniffer mode
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_start_monitor(void);
/*used in sniffer mode, close sniffer mode
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_stop_monitor(void);
/** @brief used in sniffer mode, set the sniffer channel, should call this cmd after call start_monitor cmd
*
* @param channel : WIFI channel(1-13)
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_monitor_set_channel(int channel);
/** @brief used to get current channel both in sta and ap mode
*
* @return 1-14 : channel number.
* @return 0 : no valid channel
*/
int lega_wlan_get_channel(void);
/** @brief used in sta mode, set the ps bc mc and listen interval, called before connect to ap.
*
* @param listen_bc_mc : true or false
* @param listen_interval :1, 3, 10
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_set_ps_options(uint8_t listen_bc_mc, uint16_t listen_interval);
/** @brief used in sta mode, set ps mode on/off
*
* @param ps_on : true or false
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_set_ps_mode(uint8_t ps_on);
/*when use monitor mode, user should register this type of callback function to get the received MPDU*/
typedef void (*monitor_cb_t)(uint8_t*data, int len, int rssi);
/*when use monitor-ap mode, user should register this type of callback function */
typedef void (*monitor_ap_cb_t)();
/** @brief used in sniffer mode, callback function to get received MPDU, should register before start_monitor
*
* @param fn : refer to monitor_data_cb_t
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_register_monitor_cb(monitor_cb_t fn);
/** @brief used in sniffer-ap mode, callback function for application
*
* @param fn : refer to monitor_ap_cb_t
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_register_monitor_ap_cb(monitor_ap_cb_t fn);
/* start adv callback function, notify the connect results*/
typedef void (*start_adv_cb_t)(lega_start_adv_results_e status);
/** @brief used in sta mode, callback function to notify the connecting results
*
* @param fn : refer to start_adv_cb_t
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_register_start_adv_cb(start_adv_cb_t fn);
/** @brief used in station mode or sniffer mode, call this cmd to send a MPDU constructed by user
*
* @param buf : mac header pointer of the MPDU
* @param len : length of the MPDU
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_send_raw_frame(uint8_t *buf, int len);
/*enable WIFI stack log, will be output by uart
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_start_debug_mode(void);
/*disable WIFI stack log
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_stop_debug_mode(void);
/*
* The event callback function called at specific wifi events occurred by wifi stack.
* user should register these callback if want to use the informatin.
*
* @note For HAL implementors, these callbacks must be
* called under normal task context, not from interrupt.
*/
typedef void (*lega_wlan_cb_ip_got)(lega_wlan_ip_stat_t *ip_status);
/** @brief used in station mode, WIFI stack call this cb when get ip
*
* @param fn : cb function type, refer to lega_wlan_ip_stat_t
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_ip_got_cb_register(lega_wlan_cb_ip_got fn);
typedef void (*lega_wlan_cb_stat_chg)(lega_wifi_event_e wlan_event);
/** @brief used in station and softap mode,
* WIFI stack call this cb when status change, refer to lega_wifi_event_e
*
* @param fn : cb function type
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_stat_chg_cb_register(lega_wlan_cb_stat_chg fn);
typedef void (*lega_wlan_cb_scan_compeleted)(lega_wlan_scan_result_t *result);
/** @brief used in station mode,
* WIFI stack call this cb when scan complete
*
* @param fn : cb function type
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_scan_compeleted_cb_register(lega_wlan_cb_scan_compeleted fn);
typedef void (*lega_wlan_cb_associated_ap)(lega_wlan_ap_info_adv_t *ap_info);
/** @brief used in station mode,
* WIFI stack call this cb when associated with an AP, and tell the AP information
*
* @param fn : cb function type
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_associated_ap_cb_register(lega_wlan_cb_associated_ap fn);
/** @brief calibration RCO clock for RTC
*
*/
void lega_drv_rco_cal(void);
/** @brief config to close DCDC PFM mode
*
*/
void lega_drv_close_dcdc_pfm(void);
/** @brief config to support smartconfig in MIMO scenario
*
*/
void lega_wlan_smartconfig_mimo_enable(void);
/** @brief set country code to update country code, different country may have different channel list
* called after hal_wifi_init
*/
void lega_wlan_set_country_code(char *country);
/** @brief start monitor and ap coexist mode
*
* @param init_info : refer to lega_wlan_init_type_t
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_start_monitor_ap(lega_wlan_init_type_t* init_info);
/** @brief stop monitor and ap coexist mode
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_stop_monitor_ap();
/** @brief get current temperature (C degree)
* called after hal_wifi_init
*
* @param p_temp : input param to get temperature, memory managed by caller
*
* @return 0 : on success.
* @return other : error occurred
*/
int16_t lega_rf_get_temperature(int16_t *p_temp);
/* temperature get callback function, notify the current temperature*/
typedef void (*temperature_get_cb_t)(int16_t temperature);
/** @brief set the timer to get temperature (in second)
* called after hal_wifi_init
*
* @param timer_in_sec : the timer in second
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_set_temperature_get_timer(uint64_t timer_in_sec);
/** @brief register the temperature get callback function
* called after hal_wifi_init
*
* @param func : the function will called to notify the temperature.
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_register_temperature_get_cb(temperature_get_cb_t func);
/* efuse info update callback function, pass customer efuse info to ASR*/
typedef void (*efuse_info_update_cb_t)(efuse_info_t *efuse_info);
/** @brief register the efuse info update callback function if efuse layout not same as ASR
* called before hal_wifi_init
*
* @param func : the function will be called to pass customer efuse info to ASR.
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_register_efuse_info_update_cb(efuse_info_update_cb_t func);
#endif //_LEGA_WIFI_API_H_

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#ifndef _LEGA_WIFI_API_AOS_H_
#define _LEGA_WIFI_API_AOS_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "lega_wlan_api.h"
typedef enum
{
WLAN_EVENT_SCAN_COMPLETED,
WLAN_EVENT_ASSOCIATED,
WLAN_EVENT_CONNECTED,
WLAN_EVENT_IP_GOT,
WLAN_EVENT_DISCONNECTED,
WLAN_EVENT_AP_UP,
WLAN_EVENT_AP_DOWN,
WLAN_EVENT_MAX,
}lega_wlan_event_e;
/**
* @brief Input network precise paras in lega_wlan_start_adv function.
*/
typedef struct
{
lega_wlan_ap_info_adv_t ap_info; /**< @ref apinfo_adv_t. */
char key[64]; /**< Security key or PMK of the wlan. */
int key_len; /**< The length of the key. */
char local_ip_addr[16]; /**< Static IP configuration, Local IP address. */
char net_mask[16]; /**< Static IP configuration, Netmask. */
char gateway_ip_addr[16]; /**< Static IP configuration, Router IP address. */
char dns_server_ip_addr[16]; /**< Static IP configuration, DNS server IP address. */
char dhcp_mode; /**< DHCP mode, @ref DHCP_Disable, @ref DHCP_Client and @ref DHCP_Server. */
char reserved[32];
int wifi_retry_interval; /**< Retry interval if an error is occured when connecting an access point,
time unit is millisecond. */
} lega_wlan_init_info_adv_st;
/** @brief used in station and softap mode, get mac address(in char mode) of WIFI device
*
* @param mac_addr : pointer to get the mac address
*
* @return 0 : on success.
* @return other : error occurred
*/
int lega_wlan_get_mac_address_inchar(char *puc_mac);
int lega_wlan_suspend_sta(void);
int lega_wlan_suspend_ap(void);
int lega_wlan_suspend(void);
void lega_wlan_register_mgmt_monitor_cb(monitor_cb_t fn);
/*Wifi event callback interface
*
* @return void
*/
extern void wifi_event_cb(lega_wlan_event_e evt, void* info);
#ifdef __cplusplus
}
#endif
#endif //_LEGA_WIFI_API_AOS_H_

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/*
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#ifndef __CC_H__
#define __CC_H__
#include "stdio.h"
#include "stdlib.h"
#include <sys/time.h>
#define LWIP_MAILBOX_QUEUE 1
#define LWIP_TIMEVAL_PRIVATE 0
#define LWIP_NO_INTTYPES_H 1
#if LWIP_NO_INTTYPES_H
#define X8_F "02x"
#define U16_F "u"
#define S16_F "d"
#define X16_F "x"
#define U32_F "u"
#define S32_F "d"
#define X32_F "x"
#define SZT_F U32_F
#endif
/* define compiler specific symbols */
#if defined (__ICCARM__)
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#define PACK_STRUCT_USE_INCLUDES
#elif defined (__CC_ARM)
#define PACK_STRUCT_BEGIN __packed
#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#elif defined (__GNUC__)
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_STRUCT __attribute__ ((packed))
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#elif defined (__TASKING__)
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#endif
#ifndef LWIP_PLATFORM_ASSERT
#define LWIP_PLATFORM_ASSERT(x) \
do \
{ printf("Assertion \"%s\" failed at line %d in %s\n", x, __LINE__, __FILE__); \
} while(0)
#endif
#ifndef LWIP_PLATFORM_DIAG
#define LWIP_PLATFORM_DIAG(x) do {printf x ;} while(0)
#endif
// cup byte order
#ifndef BYTE_ORDER
#define BYTE_ORDER LITTLE_ENDIAN
#endif
#define LWIP_RAND() ((u32_t)rand())
#endif /* __CC_H__ */

322
Living_SDK/board/asr5501/drivers/include/lwip_if/lwipopts.h Normal file
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/**
* @file
*
* lwIP Options Configuration
*/
/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#ifndef LWIP_LWIPOPTS_H
#define LWIP_LWIPOPTS_H
#include "lwip/arch.h"
#define LWIP_NETIF_API 1
#define LWIP_PRIVATE_FD_SET
/**
* Include user defined options first. Anything not defined in these files
* will be set to standard values. Override anything you dont like!
*/
#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1
/*
-------------- NO SYS --------------
*/
#define NO_SYS 0
#define SYS_LIGHTWEIGHT_PROT (NO_SYS == 0)
#ifndef LWIP_NETIF_API
#define LWIP_NETIF_API 1
#endif
/*
---------- Memory options ----------
*/
#define MEM_ALIGNMENT 4
#define MEM_SIZE (3*1024) //(10*1024)
#define MEM_LIBC_MALLOC 1
#if MEM_LIBC_MALLOC
#include <aos/kernel.h>
#define mem_clib_malloc aos_malloc
#define mem_clib_free aos_free
#define mem_clib_calloc(n, m) aos_zalloc( (n) * (m) )
#endif
#define MEMP_MEM_MALLOC 1
#define MEMP_OVERFLOW_CHECK 1
/*
---------- Internal Memory Pool Sizes ----------
*/
#define MEMP_NUM_PBUF 8
#define MEMP_NUM_RAW_PCB 8
#define MEMP_NUM_UDP_PCB 8
#define MEMP_NUM_TCP_PCB 8
#define MEMP_NUM_TCP_PCB_LISTEN 8
#define MEMP_NUM_TCP_SEG 12
#define MEMP_NUM_REASSDATA 4
#define MEMP_NUM_FRAG_PBUF 8
#define MEMP_NUM_ARP_QUEUE 8
#define MEMP_NUM_NETBUF 8
#define MEMP_NUM_NETCONN 10
#define MEMP_NUM_TCPIP_MSG_API 8
#define MEMP_NUM_TCPIP_MSG_INPKT 12
#define PBUF_POOL_SIZE 10
/*
---------- ARP options ----------
*/
#define LWIP_ARP 1
/*
---------- IP options ----------
*/
#define LWIP_IPV4 1
#define LWIP_IPV6 0
#define IP_FORWARD 0
#define IP_OPTIONS_ALLOWED 1
#define IP_REASSEMBLY 0
#define IP_FRAG 0
#define IP_REASS_MAXAGE 3
#define IP_REASS_MAX_PBUFS 4
#define IP_FRAG_USES_STATIC_BUF 0
#define IP_DEFAULT_TTL 255
/*
---------- ICMP options ----------
*/
#define LWIP_ICMP 1
#define LWIP_ICMP6 1
#define CHECKSUM_CHECK_ICMP6 0
#define LWIP_MULTICAST_PING 1
/*
---------- RAW options ----------
*/
#define LWIP_RAW 1
/*
---------- DHCP options ----------
*/
#define LWIP_DHCP 1
#define LWIP_NETIF_STATUS_CALLBACK 1
#define DHCP_DOES_ARP_CHECK 0
/*
---------- AUTOIP options ----------
*/
#define LWIP_AUTOIP 0
/*
---------- SNMP options ----------
*/
#define LWIP_SNMP 0
/*
---------- IGMP options ----------
*/
#define LWIP_IGMP 1
/*
---------- DNS options -----------
*/
#define LWIP_DNS 1
/*
---------- UDP options ----------
*/
#define LWIP_UDP 1
/*
---------- TCP options ----------
*/
#define LWIP_TCP 1
#define LWIP_LISTEN_BACKLOG 0
#define TCP_MSS 1460 //1792
#define TCP_WND (2 * TCP_MSS)
#define TCP_SND_BUF (4 * TCP_MSS)
#define TCP_MAXRTX 12
#define TCP_SYNMAXRTX 12
/*
---------- Pbuf options ----------
*/
#define PBUF_LINK_HLEN 16
//#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN)
#define PBUF_POOL_BUFSIZE 512 //1500
/*
---------- Network Interfaces options ----------
*/
#ifdef CHECKSUM_BY_HARDWARE
/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 0
/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 0
/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 0
/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 0
/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 0
/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 0
#define CHECKSUM_GEN_ICMP 0
#else
/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 1
/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 1
/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 1
/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 1
/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 1
/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 1
#endif
/*
---------- LOOPIF options ----------
*/
#define LWIP_NETIF_LOOPBACK 1
#define LWIP_HAVE_LOOPIF 1
#define LWIP_NETIF_LOOPBACK_MULTITHREADING 1
#define LWIP_LOOPBACK_MAX_PBUFS 8
/*
---------- Thread options ----------
*/
#define TCPIP_MBOX_SIZE 60
#define DEFAULT_ACCEPTMBOX_SIZE 10
#define DEFAULT_RAW_RECVMBOX_SIZE 10
#define DEFAULT_UDP_RECVMBOX_SIZE 20
#define DEFAULT_TCP_RECVMBOX_SIZE 10
#define LWIP_TCPIP_CORE_LOCKING 0
#define LWIP_TCPIP_CORE_LOCKING_INPUT 0
#define ETHIF_IN_TASK_STACKSIZE 512 /* unit 4 byte */
#define ETHIF_IN_TASK_PRIO 10
#define TCPIP_THREAD_STACKSIZE 2048//10240/* unit 4 byte */
#define TCPIP_THREAD_PRIO 4//0
/*
---------- Sequential layer options ----------
*/
#define LWIP_NETCONN 8
/*
---------- Socket options ----------
*/
#define LWIP_SOCKET 1
#define LWIP_COMPAT_SOCKETS 1
#define LWIP_POSIX_SOCKETS_IO_NAMES 1
#if !defined(FD_SET) && defined(RHINO_CONFIG_VFS_DEV_NODES)
#define LWIP_SOCKET_OFFSET RHINO_CONFIG_VFS_DEV_NODES
#endif
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVTIMEO 1
#define SO_REUSE 1
/*
---------- Statistics options ----------
*/
#define LWIP_STATS 1
#define LWIP_STATS_DISPLAY 1
/*
---------- Checksum options ----------
*/
/*
---------- IPv6 options ---------------
*/
/*
---------- Hook options ---------------
*/
#ifdef CONFIG_AOS_MESH
#define LWIP_DECLARE_HOOK \
struct netif *lwip_hook_ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest); \
int lwip_hook_mesh_is_mcast_subscribed(const ip6_addr_t *dest);
#define LWIP_HOOK_IP6_ROUTE(src, dest) lwip_hook_ip6_route(src, dest)
#define LWIP_HOOK_MESH_IS_MCAST_SUBSCRIBED(dest) lwip_hook_mesh_is_mcast_subscribed(dest)
#endif
/*
---------- Debugging options ----------
*/
//#define LWIP_DEBUG 1
#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL
#define LWIP_DBG_TYPES_ON (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH|LWIP_DBG_HALT)
#define MEM_DEBUG LWIP_DBG_OFF
#define MEMP_DEBUG LWIP_DBG_OFF
#define PBUF_DEBUG LWIP_DBG_OFF
#define API_LIB_DEBUG LWIP_DBG_ON
#define API_MSG_DEBUG LWIP_DBG_ON
#define TCPIP_DEBUG LWIP_DBG_OFF
#define NETIF_DEBUG LWIP_DBG_OFF
#define SOCKETS_DEBUG LWIP_DBG_ON
#define IP_DEBUG LWIP_DBG_OFF
#define IP_REASS_DEBUG LWIP_DBG_OFF
#define RAW_DEBUG LWIP_DBG_OFF
#define ICMP_DEBUG LWIP_DBG_OFF
#define UDP_DEBUG LWIP_DBG_OFF
#define TCP_DEBUG LWIP_DBG_OFF
#define TCP_INPUT_DEBUG LWIP_DBG_ON
#define TCP_OUTPUT_DEBUG LWIP_DBG_ON
#define TCP_RTO_DEBUG LWIP_DBG_OFF
#define TCP_CWND_DEBUG LWIP_DBG_OFF
#define TCP_WND_DEBUG LWIP_DBG_OFF
#define TCP_FR_DEBUG LWIP_DBG_OFF
#define TCP_QLEN_DEBUG LWIP_DBG_OFF
#define TCP_RST_DEBUG LWIP_DBG_OFF
/*
---------- Performance tracking options ----------
*/
/*
---------- PPP options ----------
*/
#define PPP_SUPPORT 0
#define LWIP_NETCONN_SEM_PER_THREAD 1
#endif /* LWIP_LWIPOPTS_H */

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/**
******************************************************************************
*
* @file system_version.h
*
* @brief lega version info provide
*
* Copyright (C) ASR
*
******************************************************************************
*/
#ifndef __SYSTEM_VERSION_H__
#define __SYSTEM_VERSION_H__
/**
* Get wifi version.
*
* @return wifi version success, 0 failure.
*/
const char *lega_get_wifi_version(void);
#endif //__SYSTEM_VERSION_H__

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/*
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x08040000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x10000; /* required amount of heap */
_Min_Stack_Size = 0x2000; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (xr) : ORIGIN = 0x00040000, LENGTH = 1024K
RAM(rw) : ORIGIN = 0x08000000, LENGTH = 256K
SHARED_MEMORY(rw) : ORIGIN = 0x60000000, LENGTH = 128K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = 0xA0;
} >FLASH
.app_version_sec :
{
KEEP(*(app_version_sec))
. = ALIGN(0x10);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
*(seg_flash_driver);
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT>FLASH
/* shared RAM */
SHAREDRAM ORIGIN(SHARED_MEMORY):
{
. = ALIGN(4);
*ipc_shared.o(COMMON)
*hal_desc.o(COMMON)
*txl_buffer_shared.o(COMMON)
*txl_frame_shared.o(COMMON)
*scan_shared.o(COMMON)
*scanu_shared.o(COMMON)
. = ALIGN(4);
} >SHARED_MEMORY AT>FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
/* User_heap_stack section, used to check that there is enough RAM left */
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
/* system stack */
PROVIDE (_stack_base = _estack - _Min_Stack_Size); /* _estack is top of stack*/
ASSERT ((_stack_base > end), "Error: No room left for the stack")
/* _estack is top of stack*/
/* left ram for heap */
PROVIDE (heap_start = _end);
PROVIDE (heap_end = _stack_base);
PROVIDE (heap_len = heap_end - heap_start);
ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap")
.ARM.attributes 0 : { *(.ARM.attributes) }
}

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/*
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x08038000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x10000; /* required amount of heap */
_Min_Stack_Size = 0x2000; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (xr) : ORIGIN = 0x10040000, LENGTH = 768K
RAM(rw) : ORIGIN = 0x08000000, LENGTH = 224K
SHARED_MEMORY(rw) : ORIGIN = 0x60000000, LENGTH = 32K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = 0x100;
} >FLASH
.app_version_sec :
{
KEEP(*(app_version_sec))
. = ALIGN(0x10);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
*(seg_flash_driver);
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT>FLASH
/* shared RAM */
/* shared RAM */
sharemem(NOLOAD):
{
. = ALIGN(4);
_shmem_s = .;
*(SHAREDRAM)
. = ALIGN(4);
_shmem_e = .;
} >SHARED_MEMORY
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
/* User_heap_stack section, used to check that there is enough RAM left */
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
/* system stack */
PROVIDE (_stack_base = _estack - _Min_Stack_Size); /* _estack is top of stack*/
ASSERT ((_stack_base > end), "Error: No room left for the stack")
/* _estack is top of stack*/
/* left ram for heap */
PROVIDE (heap_start = _end);
PROVIDE (heap_end = _stack_base);
PROVIDE (heap_len = heap_end - heap_start);
ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap")
.ARM.attributes 0 : { *(.ARM.attributes) }
}

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#include <stdio.h>
#include "board.h"
#include "lega_cm4.h"
#include "lega_common.h"
#include "systick_delay.h"
#include "lega_uart.h"
#include "lega_wdg.h"
#include "lega_flash.h"
#include "lega_common.h"
#include "lega_wlan_api.h"
#define SYS_APP_VERSION_SEG __attribute__((section("app_version_sec")))
SYS_APP_VERSION_SEG const char app_version[] = SYSINFO_APP_VERSION;
extern hal_wifi_module_t sim_aos_wifi_lega;
extern void NVIC_init();
extern int soc_pre_init(void);
#ifdef ALIOS_SUPPORT
extern void ota_roll_back_pro(void);
#endif
static void wifi_common_init()
{
printf("start------wifi_hal\r\n");
hal_wifi_register_module(&sim_aos_wifi_lega);
hal_wifi_init();
}
/***********************************************************
* init IRQ, set priority and enable IRQ
*
**********************************************************/
void NVIC_init()
{
//set irq priority, default set configLIBRARY_NORMAL_INTERRUPT_PRIORITY
NVIC_SetPriority(UART0_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(UART1_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(UART2_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(CEVA_RW_IP_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(D_APLL_UNLOCK_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(D_SX_UNLOCK_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(SLEEP_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(WDG_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(FLASH_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(GPIO_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(TIMER_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(CRYPTOCELL310_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(DMA_CTRL_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(SPI0_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(SPI1_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(SPI2_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(I2C0_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(I2C1_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(SDIO_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
NVIC_SetPriority(PLF_WAKEUP_IRQn,configLIBRARY_NORMAL_INTERRUPT_PRIORITY);
}
#ifdef ALIOS_SUPPORT
uart_dev_t uart_0;
void hal_uart1_callback_handler(char ch);
#endif
void uart_init(void)
{
#ifdef ALIOS_SUPPORT
//uart_0.port=LEGA_UART1_INDEX;
uart_0.port = PORT_UART_STD; /*logic port*/
#ifdef HIGHFREQ_MCU160_SUPPORT
uart_0.config.baud_rate=UART_BAUDRATE_1000000;
#else
uart_0.config.baud_rate=UART_BAUDRATE_115200;
#endif
uart_0.config.data_width = DATA_8BIT;
uart_0.config.flow_control = FLOW_CTRL_DISABLED;
uart_0.config.parity = PARITY_NO;
uart_0.config.stop_bits = STOP_1BIT;
//uart_0.priv = (void *)(hal_uart1_callback_handler);
hal_uart_init(&uart_0);
#endif
}
#ifdef HIGHFREQ_MCU160_SUPPORT
//all peripheral reinit code should place here
void peripheral_reinit(void)
{
uart_init();
}
#endif
#ifdef SYSTEM_RECOVERY
lega_wdg_dev_t lega_wdg;
void wdg_init(void)
{
lega_wdg.port = 0;
lega_wdg.config.timeout = WDG_TIMEOUT_MS;
lega_wdg_init(&lega_wdg);
}
#endif
/***********************************************************
* init device, such as irq, system clock, uart
**********************************************************/
uint32_t system_bus_clk = SYSTEM_BUS_CLOCK_INIT;
uint32_t system_core_clk = SYSTEM_CORE_CLOCK_INIT;
void lega_devInit()
{
#ifdef _SPI_FLASH_ENABLE_
lega_flash_init();
#endif
#ifdef ALIOS_SUPPORT
ota_roll_back_pro();
#endif
#ifdef SYSTEM_RECOVERY
wdg_init();
#endif
NVIC_init();
#ifdef DCDC_PFMMODE_CLOSE
lega_drv_close_dcdc_pfm();
#endif
lega_drv_rco_cal();
SysTick_Config(SYSTEM_CORE_CLOCK/RHINO_CONFIG_TICKS_PER_SECOND);
//init uart
uart_init();
#ifdef CFG_MIMO_UF
//config to support smartconfig in MIMO scenario
//lega_wlan_smartconfig_mimo_enable();
#endif
#ifdef ALIOS_SUPPORT
hw_start_hal();
#endif
}
/**************************************************
* after task run use board_sys_init to init board
**************************************************/
int board_after_init(void)
{
lega_devInit();
//hw_start_hal();
//NVIC_init();
tcpip_init( NULL, NULL );
wifi_common_init();
//init_uwifi();
return 0;
}
/**************************************************
* before task run use board_sys_init to init board
**************************************************/
void board_init(void)
{
#ifdef LEGA_A0V1
// Clear RFA Only Mode
REG_PMU_CTRL &= ~ENABLE_RFA_DEBUG;
REG_WR(SYS_REG_BASE_FLASH_CLK, 0x01); //26MHz flash,default 13MHz
#endif
flash_partition_init();
}

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/*
* Copyright (C) 2015-2019 Alibaba Group Holding Limited
*/
#include "aos/init.h"
#include "board.h"
#include <k_api.h>
#include <stdio.h>
#include <stdlib.h>
#include "lega_cm4.h"
#include "systick_delay.h"
/*
main task stask size(byte)
*/
#define OS_MAIN_TASK_STACK (4096/4)
#define OS_MAIN_TASK_PRI 32
/* For user config
kinit.argc = 0;
kinit.argv = NULL;
kinit.cli_enable = 1;
*/
static kinit_t kinit = {0, NULL, 1};
static ktask_t *g_main_task;
extern void board_init(void);
static void sys_init(void)
{
board_after_init();
/*aos components init including middleware and protocol and so on !*/
aos_kernel_init(&kinit);
}
void HCLK_SW_IRQHandler(void)
{
SYS_CRM_CLR_HCLK_REC = 0x1;
}
void delay_nop(unsigned int dly)
{
volatile unsigned int i;
for(i=dly; i>0; i--)
{
}
}
void ahb_sync_brid_open(void)
{
unsigned int is_using_sync_down = (REG_AHB_BUS_CTRL & (0x1<<1));
if(!is_using_sync_down)
{
REG_AHB_BUS_CTRL |= (0x1<<1); //0x40000A90 bit1 sw_use_hsync
__enable_irq();
NVIC_EnableIRQ(24);
__asm volatile("DSB");
__asm volatile("WFI");
__asm volatile("ISB");
delay_nop(50);
}
}
int main(void)
{
ahb_sync_brid_open();
lega_flash_alg_cache_flush();
board_init();
/*kernel init, malloc can use after this!*/
krhino_init();
/*main task to run */
krhino_task_dyn_create(&g_main_task, "main_task", 0, OS_MAIN_TASK_PRI, 0, OS_MAIN_TASK_STACK, (task_entry_t)sys_init, 1);
/*kernel start schedule!*/
krhino_start();
/*never run here*/
return 0;
}

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/************************** startup_cm4.s **********************************************/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word intc_irq /* intc_irq CEVA RW IP Interrupt */
.word SLEEP_IRQHandler /* Sleep Wake-Up Interrupt */
.word WDG_IRQHandler /* Window WatchDog */
.word FLASH_IRQHandler /* FLASH */
.word GPIO_IRQHandler /* GPIO */
.word TIMER_IRQHandler /* Timer interrupt */
.word CRYPTOCELL310_IRQHandler /* CryptoCell 310 Interrupt */
.word DMA_CTRL_IRQHandler /* Generic DMA Ctrl Interrupt */
.word UART0_IRQHandler /* UART0 Interrupt */
.word UART1_IRQHandler /* UART1 Interrupt */
.word UART2_IRQHandler /* UART2 Interrupt */
.word SPI0_IRQHandler /* SPI0 */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word I2C0_IRQHandler /* I2C0 */
.word I2C1_IRQHandler /* I2C1 */
.word SDIO_IRQHandler /* SDIO Combined Interrupt */
.word D_APLL_UNLOCK_IRQHandler /* RF added: D_APLL_UNLOCK */
.word D_SX_UNLOCK_IRQHandler /* RF added: D_SX_UNLOCK */
.word 0x00000000
.word 0x00000000
.word 0x00000000
.word 0x00000000
.word PLATFORM_WAKEUP_IRQHandler /*!< WiFi SOC Wake-Up Interrupt */
.word HCLK_SW_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak intc_irq
.thumb_set intc_irq,Default_Handler
.weak SLEEP_IRQHandler
.thumb_set SLEEP_IRQHandler,Default_Handler
.weak WDG_IRQHandler
.thumb_set WDG_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak GPIO_IRQHandler
.thumb_set GPIO_IRQHandler,Default_Handler
.weak TIMER_IRQHandler
.thumb_set TIMER_IRQHandler,Default_Handler
.weak CRYPTOCELL310_IRQHandler
.thumb_set CRYPTOCELL310_IRQHandler,Default_Handler
.weak DMA_CTRL_IRQHandler
.thumb_set DMA_CTRL_IRQHandler,Default_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Default_Handler
.weak UART1_IRQHandler
.thumb_set UART1_IRQHandler,Default_Handler
.weak UART2_IRQHandler
.thumb_set UART2_IRQHandler,Default_Handler
.weak SPI0_IRQHandler
.thumb_set SPI0_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak I2C0_IRQHandler
.thumb_set I2C0_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak D_APLL_UNLOCK_IRQHandler
.thumb_set D_APLL_UNLOCK_IRQHandler,Default_Handler
.weak D_SX_UNLOCK_IRQHandler
.thumb_set D_SX_UNLOCK_IRQHandler,Default_Handler
.weak PLATFORM_WAKEUP_IRQHandler
.thumb_set PLATFORM_WAKEUP_IRQHandler,Default_Handler
.weak HCLK_SW_IRQHandler
.thumb_set HCLK_SW_IRQHandler,Default_Handler
/*****************END OF FILE*********************/

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Living_SDK/board/asr5501/ucube.py Executable file
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linux_only_targets="living_platform linkkit_gateway smart_outlet smart_outlet_meter smart_led_bulb smart_led_strip"

11
Living_SDK/board/b_l475e/atcmd_config_platform.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef _ATCMD_CONFIG_PLATFORM_H_
#define _ATCMD_CONFIG_PLATFORM_H_
// AT uart
#define AT_UART_PORT 1
#endif

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Living_SDK/board/b_l475e/b_l475e.mk Normal file
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NAME := board_b_l475e
JTAG := stlink-v2-1
$(NAME)_TYPE := kernel
MODULE := 1062
HOST_ARCH := Cortex-M4
HOST_MCU_FAMILY := stm32l475
SUPPORT_BINS := no
$(NAME)_SOURCES := board.c osa_flash.c
GLOBAL_INCLUDES += .
GLOBAL_DEFINES += STDIO_UART=0
GLOBAL_DEFINES += RHINO_CONFIG_TICK_TASK=0
GLOBAL_DEFINES += RHINO_CONFIG_WORKQUEUE=1
sal ?= 1
ifeq (1,$(sal))
$(NAME)_COMPONENTS += sal
module ?= wifi.mk3060
else
GLOBAL_DEFINES += CONFIG_NO_TCPIP
endif
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_B-L475E
CONFIG_SYSINFO_DEVICE_NAME := B-L475E
GLOBAL_CFLAGS += -DSYSINFO_OS_VERSION=\"$(CONFIG_SYSINFO_OS_VERSION)\"
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
ifeq ($(COMPILER),armcc)
else ifeq ($(COMPILER),iar)
else
GLOBAL_LDFLAGS += -L $(SOURCE_ROOT)/board/b_l475e
endif
# Global defines
# HSE_VALUE = STM32 crystal frequency = 26MHz (needed to make UART work correctly)
GLOBAL_DEFINES += $$(if $$(NO_CRLF_STDIO_REPLACEMENT),,CRLF_STDIO_REPLACEMENT)
GLOBAL_CFLAGS += -DSTM32L475xx
WIFI_FIRMWARE_SECTOR_START := 2 #0x2000
FILESYSTEM_IMAGE_SECTOR_START := 256 #0x100000
# Extra build target in mico_standard_targets.mk, include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
EXTRA_TARGET_MAKEFILES += $(MAKEFILES_PATH)/aos_standard_targets.mk
#EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk
# Define default component testcase for certification
ifneq (, $(findstring yts, $(BUILD_STRING)))
TEST_COMPONENTS += basic rhino yloop api kv
TEST_COMPONENTS += cjson list digest_algorithm hashtable
TEST_COMPONENTS += netmgr wifi_hal
TEST_COMPONENTS += http cloudcoap
endif

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#include "hal/soc/soc.h"
#include <aos/kernel.h>
/* Logic partition on flash devices */
hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX];
void board_init(void)
{
hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_APPLICATION].partition_description = "Application";
hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = 0x08000000;
hal_partitions[HAL_PARTITION_APPLICATION].partition_length = 0x7D000; //500k bytes
hal_partitions[HAL_PARTITION_APPLICATION].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = "PARAMETER1";
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = 0x0807D000;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = 0x1000; // 4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = "PARAMETER2";
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = 0x0807E000;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_description = "OTA Storage";
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_start_addr = 0x08080000;
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_length = 0x7D000; //500k bytes
hal_partitions[HAL_PARTITION_OTA_TEMP].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_description = "PARAMETER3";
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_start_addr = 0x080FD000;
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_3].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_description = "PARAMETER4";
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_start_addr = 0x080FE000;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
}

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#define HARDWARE_REVISION "V1.0"
#define MODEL "STM32L4"
#ifdef BOOTLOADER
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#else
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#endif

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Living_SDK/board/b_l475e/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 0
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 100
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#endif /* CONFIG_H */

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#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "stm32l4xx_hal.h"
#include "stm32l4xx_hal_flash.h"
#define EN_DBG 0
#define KM_FLASH_ADDR_START 0x080FF000
#define KM_FLASH_ADDR_SIZE 0x1000
#define FLASH_BLOCK_LEN FLASH_PAGE_SIZE
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t Addr)
{
uint32_t page = 0;
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
/* Bank 1 */
page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE;
}
else
{
/* Bank 2 */
page = (Addr - (FLASH_BASE + FLASH_BANK_SIZE)) / FLASH_PAGE_SIZE;
}
return page;
}
/**
* @brief Gets the bank of a given address
* @param Addr: Address of the FLASH Memory
* @retval The bank of a given address
*/
static uint32_t GetBank(uint32_t Addr)
{
uint32_t bank = 0;
if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
{
/* No Bank swap */
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
bank = FLASH_BANK_1;
}
else
{
bank = FLASH_BANK_2;
}
}
else
{
/* Bank swap */
if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
{
bank = FLASH_BANK_2;
}
else
{
bank = FLASH_BANK_1;
}
}
return bank;
}
int32_t osa_flash_read(void *addr, void *out, size_t size)
{
#if EN_DBG
printf("flash read addr 0x%08x size 0x%08x\n", (uint32_t)addr, size);
#endif
memcpy(out, addr ,size);
#if EN_DBG
printf("data 0x%02x 0x%02x 0x%02x 0x%02x\n",
*((uint8_t *)out + 0), *((uint8_t *)out + 1),
*((uint8_t *)out + 2), *((uint8_t *)out + 3));
#endif
return 0;
}
int32_t osa_flash_write(void *addr, void *buf, size_t size)
{
uint64_t *p = (uint64_t *)buf;
uint32_t a = (uint32_t)addr;
HAL_StatusTypeDef ret = HAL_OK;
if (0 != ((uint32_t)addr % 8) || 0 != (size % 8)) {
printf("bad param addr 0x%08x size 0x%08x\n",
(unsigned int)addr , (unsigned int)size);
return -1;
}
#if EN_DBG
printf("flash write addr 0x%08x size 0x%08x\n",
(uint32_t)addr , (uint32_t)size);
#endif
HAL_FLASH_Unlock();
while ((size >= 8) && (ret == HAL_OK)) {
ret = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, (uint32_t)a, (uint64_t)(*p));
if (0 != ret) {
printf("write flash fail addr %08x data %llx ret 0x%08x\n",
(unsigned int)a, (uint64_t)(*p), (unsigned int)ret);
return -1;
}
#if EN_DBG
uint8_t tmp_buf[8];
int i;
osa_flash_read((void *)a , tmp_buf, 8);
if (0 != memcmp(tmp_buf, p, 8)) {
printf("write than read not match \n");
for (i = 0; i < 8; ++i) {
printf("write buf 0x%02x read data 0x%02x\n", *((uint8_t *)p + i), tmp_buf[i]);
}
return -1;
}
#if 0
for (i = 0; i < 8; ++i) {
printf("write buf 0x%02x read data 0x%02x\n", *((uint8_t *)p + i), tmp_buf[i]);
}
#endif
#endif
p = (uint64_t *)((uint32_t)p + 8);
a += 8;
size -= 8;
}
HAL_FLASH_Lock();
return 0;
}
int32_t osa_flash_erase(void *addr, size_t size)
{
uint32_t PageError = 0;
FLASH_EraseInitTypeDef pEraseInit;
uint32_t cur_addr = (uint32_t)addr;
size_t cur_size = size;
HAL_FLASH_Unlock();
if (0 != (size % FLASH_BLOCK_LEN) || 0 != (cur_addr % FLASH_BLOCK_LEN)) {
printf("bad param addr 0x%08x size 0x%08x\n",
(unsigned int)addr, (unsigned int)size);
return -1;
}
if (0 == size) {
return 0;
}
while (cur_size > 0) {
/* Fill EraseInit structure*/
pEraseInit.TypeErase = FLASH_TYPEERASE_PAGES;
pEraseInit.Banks = GetBank(cur_addr);
pEraseInit.Page = GetPage(cur_addr);
pEraseInit.NbPages = 1;
#if EN_DBG
printf("flash erase page %d bank %d\n", GetPage(cur_addr), GetBank(cur_addr));
#endif
if (HAL_FLASHEx_Erase(&pEraseInit, &PageError) != HAL_OK)
{
printf("flash erase fail\n");
return -1;
}
cur_size -= FLASH_BLOCK_LEN;
cur_addr -= FLASH_BLOCK_LEN;
}
HAL_FLASH_Lock();
return 0;
}
int32_t getRDPLevel(uint32_t *RDPLevel)
{
FLASH_OBProgramInitTypeDef sFlashOptionBytes;
int32_t eRetStatus = 0;
if (NULL == RDPLevel) {
return -1;
}
/* Unlock the Flash to enable the flash control register access
*************/
HAL_FLASH_Unlock();
/* Clear OPTVERR bit set on virgin samples */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
/* Unlock the Options Bytes
*************************************************/
HAL_FLASH_OB_Unlock();
/* Get Option Bytes status for FLASH_BANK_1: WRP AREA_A and PCRoP
**********/
HAL_FLASHEx_OBGetConfig(&sFlashOptionBytes);
*RDPLevel = sFlashOptionBytes.RDPLevel;
/* Lock the Options Bytes
***************************************************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
return eRetStatus;
}
int32_t ConfigWRP (bool enable, bool reboot)
{
int32_t eRetStatus = 0;
uint32_t RDPlevel;
uint32_t StartPage = 0, EndPage = 0, StartBank = 0, EndBank = 0;
FLASH_OBProgramInitTypeDef psFlashOptionBytes, psFlashOptionBytes2;
eRetStatus = getRDPLevel(&RDPlevel);
if (0 != eRetStatus) {
return -1;
}
if (OB_RDP_LEVEL_2 == RDPlevel) {
return -1;
}
/* Get the number of the start and end pages */
StartPage = GetPage(KM_FLASH_ADDR_START);
EndPage = GetPage(KM_FLASH_ADDR_START + KM_FLASH_ADDR_SIZE - 1);
/* Get the bank of the start and end pages */
StartBank = GetBank(KM_FLASH_ADDR_START);
EndBank = GetBank(KM_FLASH_ADDR_START + KM_FLASH_ADDR_SIZE - 1);
if (StartBank != EndBank) {
/* cross bank not support now */
return -1;
}
/* WRP area is only on one bank */
if (StartBank == FLASH_BANK_1)
{
psFlashOptionBytes.WRPArea = OB_WRPAREA_BANK1_AREAA;
psFlashOptionBytes2.WRPArea = OB_WRPAREA_BANK1_AREAB;
}
else
{
psFlashOptionBytes.WRPArea = OB_WRPAREA_BANK2_AREAA;
psFlashOptionBytes2.WRPArea = OB_WRPAREA_BANK2_AREAB;
}
HAL_FLASH_Unlock();
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
HAL_FLASH_OB_Unlock();
HAL_FLASHEx_OBGetConfig(&psFlashOptionBytes);
HAL_FLASHEx_OBGetConfig(&psFlashOptionBytes2);
if (true == enable) {
/* Check if desired pages are not yet write protected ***********************/
if ((psFlashOptionBytes.WRPStartOffset <= StartPage) && (psFlashOptionBytes.WRPEndOffset >= (StartPage - 1)))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes.WRPEndOffset < EndPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
}
else if ((psFlashOptionBytes.WRPStartOffset <= (EndPage + 1)) && (psFlashOptionBytes.WRPEndOffset >= EndPage))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes.WRPStartOffset > StartPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
}
}
else if ((psFlashOptionBytes.WRPStartOffset > StartPage) && (psFlashOptionBytes.WRPEndOffset < EndPage))
{
/* Current area is included in pages to be write protected */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
else if ((psFlashOptionBytes2.WRPStartOffset <= StartPage) && (psFlashOptionBytes2.WRPEndOffset >= (StartPage - 1)))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes2.WRPEndOffset < EndPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset <= (EndPage + 1)) && (psFlashOptionBytes2.WRPEndOffset >= EndPage))
{
/* Current area is adjacent to pages to be write protected */
if (psFlashOptionBytes2.WRPStartOffset > StartPage)
{
/* Current area will be extended to include the pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset > StartPage) && (psFlashOptionBytes2.WRPEndOffset < EndPage))
{
/* Current area is included in pages to be write protected */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
else if (psFlashOptionBytes.WRPStartOffset > psFlashOptionBytes.WRPEndOffset)
{
/* Current area is not used => it will be configured to protect the pages */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = StartPage;
psFlashOptionBytes.WRPEndOffset = EndPage;
}
else if (psFlashOptionBytes2.WRPStartOffset > psFlashOptionBytes2.WRPEndOffset)
{
/* Current area is not used => it will be configured to protect the pages */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = StartPage;
psFlashOptionBytes2.WRPEndOffset = EndPage;
}
else
{
/* No more area available to protect the pages */
/* => Error : not possible to activate the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
} else {
/* disable */
/* Check if desired pages are already write protected ***********************/
if ((psFlashOptionBytes.WRPStartOffset == StartPage) && (psFlashOptionBytes.WRPEndOffset == EndPage))
{
/* Current area correspond to the area to disable */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = 0xFF;
psFlashOptionBytes.WRPEndOffset = 0;
}
else if ((psFlashOptionBytes.WRPStartOffset == StartPage) && (psFlashOptionBytes.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable : */
/* - End of area is bigger than the last page to un-protect */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = EndPage + 1;
}
else if ((psFlashOptionBytes.WRPStartOffset < StartPage) && (psFlashOptionBytes.WRPEndOffset == EndPage))
{
/* Current area is bigger than the area to disable : */
/* - Start of area is lower than the first page to un-protect */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = StartPage - 1;
}
else if ((psFlashOptionBytes.WRPStartOffset < StartPage) && (psFlashOptionBytes.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable */
/* - Start of area is lower than the first page to un-protect */
/* - End of area is bigger than the last page to un-protect */
if (psFlashOptionBytes2.WRPStartOffset > psFlashOptionBytes2.WRPEndOffset)
{
/* Second area of the bank can be used */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = EndPage + 1;
psFlashOptionBytes2.WRPEndOffset = psFlashOptionBytes.WRPEndOffset;
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPEndOffset = StartPage - 1;
}
else
{
/* Second area of the bank already used for WRP */
/* => Error : not possible to deactivate only the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
else if ((psFlashOptionBytes2.WRPStartOffset == StartPage) && (psFlashOptionBytes2.WRPEndOffset == EndPage))
{
/* Current area correspond to the area to disable */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = 0xFF;
psFlashOptionBytes2.WRPEndOffset = 0;
}
else if ((psFlashOptionBytes2.WRPStartOffset == StartPage) && (psFlashOptionBytes2.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable : */
/* - End of area is bigger than the last page to un-protect */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPStartOffset = EndPage + 1;
}
else if ((psFlashOptionBytes2.WRPStartOffset < StartPage) && (psFlashOptionBytes2.WRPEndOffset == EndPage))
{
/* Current area is bigger than the area to disable : */
/* - Start of area is lower than the first page to un-protect */
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = StartPage - 1;
}
else if ((psFlashOptionBytes2.WRPStartOffset < StartPage) && (psFlashOptionBytes2.WRPEndOffset > EndPage))
{
/* Current area is bigger than the area to disable */
/* - Start of area is lower than the first page to un-protect */
/* - End of area is bigger than the last page to un-protect */
if (psFlashOptionBytes.WRPStartOffset > psFlashOptionBytes.WRPEndOffset)
{
/* Second area of the bank can be used */
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPStartOffset = EndPage + 1;
psFlashOptionBytes.WRPEndOffset = psFlashOptionBytes2.WRPEndOffset;
psFlashOptionBytes2.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes2.WRPEndOffset = StartPage - 1;
}
else
{
/* Second area of the bank already used for WRP */
/* => Error : not possible to deactivate only the pages indicated */
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
}
/* Configure write protected pages */
if (psFlashOptionBytes.OptionType == OPTIONBYTE_WRP)
{
if(HAL_FLASHEx_OBProgram(&psFlashOptionBytes) != HAL_OK)
{
/* Error occurred while options bytes programming. **********************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
if (psFlashOptionBytes2.OptionType == OPTIONBYTE_WRP)
{
if(HAL_FLASHEx_OBProgram(&psFlashOptionBytes2) != HAL_OK)
{
/* Error occurred while options bytes programming. **********************/
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
eRetStatus = -1;
}
}
/* Generate System Reset to load the new option byte values ***************/
if (((psFlashOptionBytes.OptionType == OPTIONBYTE_WRP) || (psFlashOptionBytes2.OptionType == OPTIONBYTE_WRP)) && reboot)
{
HAL_FLASH_OB_Launch();
}
HAL_FLASH_OB_Lock();
HAL_FLASH_Lock();
return eRetStatus;
}
int32_t CleanProtectionWRP (void)
{
int32_t eRetStatus = 0;
uint32_t RDPlevel;
FLASH_OBProgramInitTypeDef psFlashOptionBytes;
eRetStatus = getRDPLevel(&RDPlevel);
if (0 != eRetStatus) {
return -1;
}
if (OB_RDP_LEVEL_2 == RDPlevel) {
return -1;
}
psFlashOptionBytes.OptionType = OPTIONBYTE_WRP;
psFlashOptionBytes.WRPArea = 0;//SFU_HAL_IF_PROTECT_WRP_AREA_1;
psFlashOptionBytes.WRPStartOffset = 0;
psFlashOptionBytes.WRPEndOffset = 0;
if (HAL_FLASHEx_OBProgram(&psFlashOptionBytes) != HAL_OK) {
eRetStatus = -1;
}
return eRetStatus;
}

35
Living_SDK/board/bk7231devkitc/bk7231devkitc.ld.S Normal file
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/*
* Script for GNU linker.
* Describes layout of sections, location of stack.
*
* In this case vectors are at location 0 (reset @ 0x08)
*
* +------------+ 0x00400000
* data |
* end
* |(heap) |
* . .
* . .
* |(heap limit)|
*
* |- - - - - - |
* stack bottom 256k
* +------------+
*
* +------------+ 0x0000000
* |vectors |
* | |
* |------------+
* |text |
* |data |
* | | 1024k
* +------------+
*/
/* Split memory into area for vectors and ram */
MEMORY
{
flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
ram (rwx): ORIGIN = 0x00400020, LENGTH = 256k - 32
}

29
Living_SDK/board/bk7231devkitc/bk7231devkitc.mk Normal file
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NAME := board_bk7231
JTAG := jlink
$(NAME)_TYPE := kernel
MODULE := BK7231
HOST_ARCH := ARM968E-S
HOST_MCU_FAMILY := bk7231
SUPPORT_BINS := no
$(NAME)_SOURCES := board.c
GLOBAL_INCLUDES += .
GLOBAL_DEFINES += STDIO_UART=1
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_BK7231
CONFIG_SYSINFO_DEVICE_NAME := BK7231
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
#GLOBAL_CFLAGS += -DSYSINFO_KERNEL_VERSION=\"$(CONFIG_SYSINFO_KERNEL_VERSION)\"
#GLOBAL_CFLAGS += -DSYSINFO_APP_VERSION=\"$(CONFIG_SYSINFO_APP_VERSION)\"
GLOBAL_LDS_INCLUDES += $(SOURCE_ROOT)/board/bk7231devkitc/bk7231devkitc.ld.S
# Extra build target in aos_standard_targets.mk, include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
EXTRA_TARGET_MAKEFILES += $(MAKEFILES_PATH)/aos_standard_targets.mk
EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk

186
Living_SDK/board/bk7231devkitc/board.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include "hal/soc/soc.h"
#include <aos/kernel.h>
#include <aos/aos.h>
/* Logic partition on flash devices */
const hal_logic_partition_t hal_partitions[] =
{
[HAL_PARTITION_BOOTLOADER] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Bootloader",
.partition_start_addr = 0x00000,
.partition_length = 0x10000, //64k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_APPLICATION] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Application",
.partition_start_addr = 0x00000,//phy is 0x11000
.partition_length = 0xAF000, //700k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_1] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER1",
.partition_start_addr = 0x100000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_2] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER2",
.partition_start_addr = 0x101000,
.partition_length = 0x2000, // 8k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_OTA_TEMP] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "OTA Storage",
.partition_start_addr = 0x103000,
.partition_length = 0xAF000, //700k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_3] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER3",
.partition_start_addr = 0x1B2000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_4] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER4",
.partition_start_addr = 0x1B3000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_RF_FIRMWARE] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "RF parameter",
.partition_start_addr = 0x1B4000,// rf parameter is 0x1A2000
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
};
#define KEY_BOOT 15
#define KEY_PS 14
static uint64_t elink_time = 0;
static uint64_t ps_time = 0;
static gpio_dev_t gpio_key_boot;
static gpio_dev_t gpio_key_ps;
static void key_poll_func(void *arg)
{
uint32_t level;
uint64_t diff;
hal_gpio_input_get(&gpio_key_boot, &level);
if (level == 0) {
aos_post_delayed_action(10, key_poll_func, NULL);
} else {
diff = aos_now_ms() - elink_time;
if (diff > 2000) { /* long press */
elink_time = 0;
aos_post_event(EV_KEY, CODE_BOOT, VALUE_KEY_LTCLICK);
} else if (diff > 40) { /* short press */
elink_time = 0;
aos_post_event(EV_KEY, CODE_BOOT, VALUE_KEY_CLICK);
} else {
aos_post_delayed_action(10, key_poll_func, NULL);
}
}
}
static void key_ps_func(void *arg)
{
#if 0
uint32_t level;
uint64_t diff;
hal_gpio_input_get(&gpio_key_ps, &level);
if (level == 0) {
aos_post_delayed_action(10, key_ps_func, NULL);
} else {
diff = aos_now_ms() - ps_time;
if (diff > 40) {
ps_time = 0;
aos_post_event(EV_KEY, CODE_BOOT, VALUE_KEY_PSCLICK);
}else if (diff > 2000) { /* short press */
elink_time = 0;
aos_post_event(EV_KEY, CODE_BOOT, VALUE_KEY_LPSCLICK);
} else {
aos_post_delayed_action(10, key_ps_func, NULL);
}
}
#endif
}
static void key_proc_work(void *arg)
{
aos_schedule_call(key_poll_func, NULL);
}
static void key_ps_work(void *arg)
{
aos_schedule_call(key_ps_func, NULL);
}
static void handle_elink_key(void *arg)
{
uint32_t gpio_value;
hal_gpio_input_get(&gpio_key_boot, &gpio_value);
if (gpio_value == 0 && elink_time == 0) {
elink_time = aos_now_ms();
aos_loop_schedule_work(0, key_proc_work, NULL, NULL, NULL);
}
}
static void handle_ps_key(void *arg)
{
uint32_t gpio_value;
hal_gpio_input_get(&gpio_key_ps, &gpio_value);
if (gpio_value == 0 && ps_time == 0) {
ps_time = aos_now_ms();
aos_loop_schedule_work(0, key_ps_work, NULL, NULL, NULL);
}
}
void board_init(void)
{
gpio_key_boot.port = KEY_BOOT;
gpio_key_boot.config = INPUT_PULL_UP;
hal_gpio_init(&gpio_key_boot);
hal_gpio_clear_irq(&gpio_key_boot);
hal_gpio_enable_irq(&gpio_key_boot, IRQ_TRIGGER_FALLING_EDGE, handle_elink_key, NULL);
gpio_key_ps.port = KEY_PS;
gpio_key_ps.config = INPUT_PULL_UP;
hal_gpio_init(&gpio_key_ps);
hal_gpio_clear_irq(&gpio_key_ps);
hal_gpio_enable_irq(&gpio_key_ps, IRQ_TRIGGER_FALLING_EDGE, handle_ps_key, NULL);
}
int board_cli_init(void)
{
}

14
Living_SDK/board/bk7231devkitc/board.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#define HARDWARE_REVISION "V1.0"
#define MODEL "BK7231"
#ifdef BOOTLOADER
#define STDIO_UART 1
#define STDIO_UART_BUADRATE 115200
#else
#define STDIO_UART 1
#define STDIO_UART_BUADRATE 115200
#endif

225
Living_SDK/board/bk7231devkitc/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 1
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 500
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#endif /* CONFIG_H */

13
Living_SDK/board/bk7231sdevkitc/README.md Executable file
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@ -0,0 +1,13 @@
## Overview
## Feature of Board
## Directories
```sh
bk7231sdevkitc # configuration files for board bk7231sdevkitc
```
## Board Hardware Resources
## Update log

35
Living_SDK/board/bk7231sdevkitc/bk7231sdevkitc.ld Executable file
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@ -0,0 +1,35 @@
/*
* Script for GNU linker.
* Describes layout of sections, location of stack.
*
* In this case vectors are at location 0 (reset @ 0x08)
*
* +------------+ 0x00400000
* data |
* end
* |(heap) |
* . .
* . .
* |(heap limit)|
*
* |- - - - - - |
* stack bottom 256k
* +------------+
*
* +------------+ 0x0000000
* |vectors |
* | |
* |------------+
* |text |
* |data |
* | | 1024k
* +------------+
*/
/* Split memory into area for vectors and ram */
MEMORY
{
flash (rx) : ORIGIN = 0x00010000, LENGTH = 2M - 64k
ram (rwx): ORIGIN = 0x00400020, LENGTH = 256k - 32
}

40
Living_SDK/board/bk7231sdevkitc/bk7231sdevkitc.mk Executable file
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NAME := board_bk7231s
JTAG := jlink
$(NAME)_MBINS_TYPE := kernel
$(NAME)_VERSION := 1.0.0
$(NAME)_SUMMARY := configuration for board bk7231s
MODULE := BK7231S
HOST_ARCH := ARM968E-S
HOST_MCU_FAMILY := bk7231s
SUPPORT_MBINS := no
$(NAME)_SOURCES := board.c
GLOBAL_INCLUDES += .
GLOBAL_DEFINES += CLI_CONFIG_SUPPORT_BOARD_CMD=1
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_BK7231S
CONFIG_SYSINFO_DEVICE_NAME := BK7231S
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
GLOBAL_LDS_INCLUDES += $(SOURCE_ROOT)/board/bk7231sdevkitc/bk7231sdevkitc.ld
# Extra build target include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
ifeq ($(PING_PONG_OTA),1)
EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_pingpong_bin.mk
else
EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk
endif
# Define default component testcase for certification
ifneq (, $(findstring yts, $(BUILD_STRING)))
TEST_COMPONENTS += basic rhino yloop api kv vfs
TEST_COMPONENTS += cjson list digest_algorithm hashtable
TEST_COMPONENTS += netmgr wifi_hal
TEST_COMPONENTS += http cloudcoap
endif

79
Living_SDK/board/bk7231sdevkitc/board.c Executable file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include "hal/soc/soc.h"
#include <aos/kernel.h>
#include <aos/aos.h>
/* Logic partition on flash devices */
const hal_logic_partition_t hal_partitions[] =
{
[HAL_PARTITION_BOOTLOADER] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Bootloader",
.partition_start_addr = 0x000000,
.partition_length = 0x10000, //64k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_1] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER1",
.partition_start_addr = 0x010000,// boot information need protect
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_APPLICATION] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Application",
.partition_start_addr = 0x011000,//cpu is 0x10000
.partition_length = 0xE1000, //900k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
/*reserved 52k*/
[HAL_PARTITION_OTA_TEMP] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "OTA Storage",
.partition_start_addr = 0x0FF000,//cpu is 0xF0000
.partition_length = 0xE1000, //900k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
/*protected flash size is 0~1984k. below are not protected.*/
[HAL_PARTITION_PARAMETER_2] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER2",
.partition_start_addr = 0x1F0000,
.partition_length = 0x2000, // 8k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_4] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER4",
.partition_start_addr = 0x1F2000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_RF_FIRMWARE] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "RF parameter",
.partition_start_addr = 0x1F3000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
};
void board_init(void)
{
}
int board_cli_init(void)
{
}

13
Living_SDK/board/bk7231sdevkitc/board.h Executable file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#define HARDWARE_REVISION "V1.0"
#define MODEL "BK7231S"
#define STDIO_UART 1
#define STDIO_UART_BUADRATE 115200
#define BK_UART 0
#define BK_UART_BUADRATE 115200

225
Living_SDK/board/bk7231sdevkitc/k_config.h Executable file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 1
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 500
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 400
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#endif /* CONFIG_H */

1
Living_SDK/board/bk7231sdevkitc/ucube.py Executable file
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@ -0,0 +1 @@
linux_only_targets="living_platform linkkit_gateway"

35
Living_SDK/board/bk7231udevkitc/bk7231udevkitc.ld Normal file
View file

@ -0,0 +1,35 @@
/*
* Script for GNU linker.
* Describes layout of sections, location of stack.
*
* In this case vectors are at location 0 (reset @ 0x08)
*
* +------------+ 0x00400000
* data |
* end
* |(heap) |
* . .
* . .
* |(heap limit)|
*
* |- - - - - - |
* stack bottom 256k
* +------------+
*
* +------------+ 0x0000000
* |vectors |
* | |
* |------------+
* |text |
* |data |
* | | 1024k
* +------------+
*/
/* Split memory into area for vectors and ram */
MEMORY
{
flash (rx) : ORIGIN = 0x00010000, LENGTH = 2M - 64k
ram (rwx): ORIGIN = 0x00400020, LENGTH = 256k - 32
}

31
Living_SDK/board/bk7231udevkitc/bk7231udevkitc.mk Normal file
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@ -0,0 +1,31 @@
NAME := board_bk7231u
JTAG := jlink
$(NAME)_TYPE := kernel
MODULE := BK7231U
HOST_ARCH := ARM968E-S
HOST_MCU_FAMILY := bk7231u
SUPPORT_BINS := no
$(NAME)_SOURCES := board.c
GLOBAL_INCLUDES += .
GLOBAL_DEFINES += STDIO_UART=1
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_BK7231U
CONFIG_SYSINFO_DEVICE_NAME := BK7231U
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
GLOBAL_LDS_INCLUDES += $(SOURCE_ROOT)/board/bk7231udevkitc/bk7231udevkitc.ld
# Extra build target in aos_standard_targets.mk, include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
EXTRA_TARGET_MAKEFILES += $(MAKEFILES_PATH)/aos_standard_targets.mk
ifeq ($(PING_PONG_OTA),1)
EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_pingpong_bin.mk
else
EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk
endif

79
Living_SDK/board/bk7231udevkitc/board.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include "hal/soc/soc.h"
#include <aos/kernel.h>
#include <aos/aos.h>
/* Logic partition on flash devices */
const hal_logic_partition_t hal_partitions[] =
{
[HAL_PARTITION_BOOTLOADER] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Bootloader",
.partition_start_addr = 0x000000,
.partition_length = 0x10000, //64k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_1] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER1",
.partition_start_addr = 0x010000,// boot information need protect
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_APPLICATION] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Application",
.partition_start_addr = 0x011000,//cpu is 0x10000
.partition_length = 0x113000, //1100k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
/*reserved 52k*/
[HAL_PARTITION_OTA_TEMP] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "OTA Storage",
.partition_start_addr = 0x124000,//cpu is 0xF0000
.partition_length = 0xC9000, //804k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
/*protected flash size is 0~1984k. below are not protected.*/
[HAL_PARTITION_PARAMETER_2] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER2",
.partition_start_addr = 0x1F0000,
.partition_length = 0x2000, // 8k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_PARAMETER_4] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER4",
.partition_start_addr = 0x1F2000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[HAL_PARTITION_RF_FIRMWARE] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "RF parameter",
.partition_start_addr = 0x1F3000,
.partition_length = 0x1000, // 4k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
};
void board_init(void)
{
}
int board_cli_init(void)
{
}

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#define HARDWARE_REVISION "V1.0"
#define MODEL "BK7231U"
#define STDIO_UART 1
#define STDIO_UART_BUADRATE 115200
#define BK_UART 0
#define BK_UART_BUADRATE 115200

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 1
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 500
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 400
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
#ifndef WIFI_CONFIG_LISTEN_INTERVAL
#define WIFI_CONFIG_LISTEN_INTERVAL 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#endif /* CONFIG_H */

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linux_only_targets="living_platform linkkit_gateway smart_outlet smart_outlet_meter smart_led_bulb smart_led_strip"

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/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H__
#define __MAIN_H__
/* Includes ------------------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private define ------------------------------------------------------------*/
#define SIM_DET_Pin GPIO_PIN_2
#define SIM_DET_GPIO_Port GPIOE
#define AUDIO_CTL_Pin GPIO_PIN_3
#define AUDIO_CTL_GPIO_Port GPIOE
#define PCIE_RST_Pin GPIO_PIN_13
#define PCIE_RST_GPIO_Port GPIOC
#define SECURE_IO_Pin GPIO_PIN_0
#define SECURE_IO_GPIO_Port GPIOA
#define SECURE_RST_Pin GPIO_PIN_1
#define SECURE_RST_GPIO_Port GPIOA
#define LCD_DCX_Pin GPIO_PIN_6
#define LCD_DCX_GPIO_Port GPIOA
#define WIFI_RST_Pin GPIO_PIN_0
#define WIFI_RST_GPIO_Port GPIOB
#define WIFI_WU_Pin GPIO_PIN_1
#define WIFI_WU_GPIO_Port GPIOB
#define LCD_RST_Pin GPIO_PIN_2
#define LCD_RST_GPIO_Port GPIOB
#define LCD_PWR_Pin GPIO_PIN_7
#define LCD_PWR_GPIO_Port GPIOE
#define ZIGBEE_INT_Pin GPIO_PIN_8
#define ZIGBEE_INT_GPIO_Port GPIOE
#define ZIGBEE_INT_EXTI_IRQn EXTI9_5_IRQn
#define KEY_2_Pin GPIO_PIN_9
#define KEY_2_GPIO_Port GPIOE
#define KEY_2_EXTI_IRQn EXTI9_5_IRQn
#define KEY_3_Pin GPIO_PIN_10
#define KEY_3_GPIO_Port GPIOE
#define KEY_3_EXTI_IRQn EXTI15_10_IRQn
#define KEY_1_Pin GPIO_PIN_11
#define KEY_1_GPIO_Port GPIOE
#define KEY_1_EXTI_IRQn EXTI15_10_IRQn
#define CAM_PD_Pin GPIO_PIN_13
#define CAM_PD_GPIO_Port GPIOE
#define AUDIO_RST_Pin GPIO_PIN_14
#define AUDIO_RST_GPIO_Port GPIOE
#define SECURE_CLK_Pin GPIO_PIN_15
#define SECURE_CLK_GPIO_Port GPIOE
#define HTS_LED_Pin GPIO_PIN_11
#define HTS_LED_GPIO_Port GPIOD
#define GS_LED_Pin GPIO_PIN_12
#define GS_LED_GPIO_Port GPIOD
#define ALS_LED_Pin GPIO_PIN_13
#define ALS_LED_GPIO_Port GPIOD
#define PS_LED_Pin GPIO_PIN_14
#define PS_LED_GPIO_Port GPIOD
#define COMPASS_LED_Pin GPIO_PIN_15
#define COMPASS_LED_GPIO_Port GPIOD
#define CAM_MCLK_Pin GPIO_PIN_8
#define CAM_MCLK_GPIO_Port GPIOA
#define ALS_INT_Pin GPIO_PIN_15
#define ALS_INT_GPIO_Port GPIOA
#define ALS_INT_EXTI_IRQn EXTI15_10_IRQn
#define AUDIO_WU_Pin GPIO_PIN_4
#define AUDIO_WU_GPIO_Port GPIOD
#define IRDA_CTL_Pin GPIO_PIN_5
#define IRDA_CTL_GPIO_Port GPIOD
#define IRDA_RX_Pin GPIO_PIN_6
#define IRDA_RX_GPIO_Port GPIOD
#define ZIGBEE_RST_Pin GPIO_PIN_7
#define ZIGBEE_RST_GPIO_Port GPIOD
#define USB_PCIE_SW_Pin GPIO_PIN_5
#define USB_PCIE_SW_GPIO_Port GPIOB
#define CAM_RST_Pin GPIO_PIN_8
#define CAM_RST_GPIO_Port GPIOB
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
extern "C" {
#endif
void _Error_Handler(char *, int);
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32l4xx_hal_conf.h
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_CONF_H
#define __STM32L4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
#include "main.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
#define HAL_CRC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
#define HAL_DCMI_MODULE_ENABLED
/*#define HAL_DMA2D_MODULE_ENABLED */
/*#define HAL_DFSDM_MODULE_ENABLED */
/*#define HAL_DSI_MODULE_ENABLED */
/*#define HAL_FIREWALL_MODULE_ENABLED */
/*#define HAL_GFXMMU_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LTDC_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_OPAMP_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
#define HAL_SAI_MODULE_ENABLED
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_SWPMI_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_TSC_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal Multiple Speed oscillator (MSI) default value.
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for SAI1 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/**
* @brief External clock source for SAI2 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32l4xx_hal_rcc.h"
#include "stm32l4xx_hal_rcc_ex.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32l4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32l4xx_hal_dma.h"
#include "stm32l4xx_hal_dma_ex.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32l4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32l4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32l4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32l4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32l4xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32l4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32l4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32l4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32l4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32l4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32l4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_FIREWALL_MODULE_ENABLED
#include "stm32l4xx_hal_firewall.h"
#endif /* HAL_FIREWALL_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32l4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32l4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32l4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32l4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32l4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32l4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32l4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED
#include "stm32l4xx_hal_lcd.h"
#endif /* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32l4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32l4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32l4xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32l4xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32l4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32l4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32l4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32l4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32l4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32l4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32l4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32l4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32l4xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32l4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32l4xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32l4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32l4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32l4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32l4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32l4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32l4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32l4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32l4xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32l4xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_IT_H
#define __STM32L4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#include "main.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void EXTI9_5_IRQHandler(void);
void USART2_IRQHandler(void);
void USART3_IRQHandler(void);
void EXTI15_10_IRQHandler(void);
void LPUART1_IRQHandler(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Living_SDK/board/developerkit/STM32L496.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00050000 { ; RW data
.ANY (+RW +ZI)
}
}

183
Living_SDK/board/developerkit/STM32L496VGTx_FLASH.ld Normal file
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/*
*****************************************************************************
**
** File : LinkerScript.ld
**
** Abstract : Linker script for STM32L496VGTx Device with
** 1024KByte FLASH, 320KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
**
** (c)Copyright Ac6.
** You may use this file as-is or modify it according to the needs of your
** project. Distribution of this file (unmodified or modified) is not
** permitted. Ac6 permit registered System Workbench for MCU users the
** rights to distribute the assembled, compiled & linked contents of this
** file as part of an application binary file, provided that it is built
** using the System Workbench for MCU toolchain.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20050000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(8);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(8);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(8);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(8);
} >FLASH
.ARM.extab :
{
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >FLASH
.ARM : {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
. = ALIGN(8);
} >FLASH
.preinit_array :
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
} >FLASH
.init_array :
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
} >FLASH
.fini_array :
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(8);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(8);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(8);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

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Living_SDK/board/developerkit/Src/main.c Normal file
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@ -0,0 +1,776 @@
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32l4xx_hal.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef hadc3;
CRC_HandleTypeDef hcrc;
DCMI_HandleTypeDef hdcmi;
I2C_HandleTypeDef hi2c1;
I2C_HandleTypeDef hi2c2;
I2C_HandleTypeDef hi2c3;
UART_HandleTypeDef hlpuart1;
UART_HandleTypeDef huart2;
UART_HandleTypeDef huart3;
SAI_HandleTypeDef hsai_BlockA2;
SPI_HandleTypeDef hspi1;
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_I2C3_Init(void);
static void MX_I2C1_Init(void);
static void MX_I2C2_Init(void);
static void MX_ADC3_Init(void);
static void MX_USART2_UART_Init(void);
static void MX_SPI1_Init(void);
static void MX_USART3_UART_Init(void);
static void MX_LPUART1_UART_Init(void);
static void MX_SAI2_Init(void);
static void MX_DCMI_Init(void);
static void MX_USB_OTG_FS_USB_Init(void);
static void MX_SDMMC1_Init(void);
static void MX_CRC_Init(void);
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE END PFP */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
*
* @retval None
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration----------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_I2C3_Init();
MX_I2C1_Init();
MX_I2C2_Init();
MX_ADC3_Init();
MX_USART2_UART_Init();
MX_SPI1_Init();
MX_USART3_UART_Init();
MX_LPUART1_UART_Init();
MX_SAI2_Init();
MX_DCMI_Init();
MX_USB_OTG_FS_USB_Init();
MX_SDMMC1_Init();
MX_CRC_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInit;
/**Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSICalibrationValue = 0;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
RCC_OscInitStruct.PLL.PLLN = 40;
RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_USART3
|RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_SAI2
|RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C2
|RCC_PERIPHCLK_I2C3|RCC_PERIPHCLK_USB
|RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_ADC;
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLLSAI1;
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLLSAI1;
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV2;
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK
|RCC_PLLSAI1_ADC1CLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure the Systick interrupt time
*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/8000);
/**Configure the Systick
*/
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8);
/**Enable MSI Auto calibration
*/
HAL_RCCEx_EnableMSIPLLMode();
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
}
/* ADC3 init function */
static void MX_ADC3_Init(void)
{
ADC_ChannelConfTypeDef sConfig;
/**Common config
*/
hadc3.Instance = ADC3;
hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc3.Init.LowPowerAutoWait = DISABLE;
hadc3.Init.ContinuousConvMode = DISABLE;
hadc3.Init.NbrOfConversion = 1;
hadc3.Init.DiscontinuousConvMode = DISABLE;
hadc3.Init.NbrOfDiscConversion = 1;
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc3.Init.DMAContinuousRequests = DISABLE;
hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc3.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc3) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
sConfig.SingleDiff = ADC_DIFFERENTIAL_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* CRC init function */
static void MX_CRC_Init(void)
{
hcrc.Instance = CRC;
hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
if (HAL_CRC_Init(&hcrc) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* DCMI init function */
static void MX_DCMI_Init(void)
{
hdcmi.Instance = DCMI;
hdcmi.Init.SynchroMode = DCMI_SYNCHRO_HARDWARE;
hdcmi.Init.PCKPolarity = DCMI_PCKPOLARITY_FALLING;
hdcmi.Init.VSPolarity = DCMI_VSPOLARITY_LOW;
hdcmi.Init.HSPolarity = DCMI_HSPOLARITY_LOW;
hdcmi.Init.CaptureRate = DCMI_CR_ALL_FRAME;
hdcmi.Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B;
hdcmi.Init.JPEGMode = DCMI_JPEG_DISABLE;
hdcmi.Init.ByteSelectMode = DCMI_BSM_ALL;
hdcmi.Init.ByteSelectStart = DCMI_OEBS_ODD;
hdcmi.Init.LineSelectMode = DCMI_LSM_ALL;
hdcmi.Init.LineSelectStart = DCMI_OELS_ODD;
if (HAL_DCMI_Init(&hdcmi) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* I2C1 init function */
static void MX_I2C1_Init(void)
{
hi2c1.Instance = I2C1;
hi2c1.Init.Timing = 0x10909CEC;
hi2c1.Init.OwnAddress1 = 0;
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c1.Init.OwnAddress2 = 0;
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* I2C2 init function */
static void MX_I2C2_Init(void)
{
hi2c2.Instance = I2C2;
hi2c2.Init.Timing = 0x10909CEC;
hi2c2.Init.OwnAddress1 = 0;
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c2.Init.OwnAddress2 = 0;
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* I2C3 init function */
static void MX_I2C3_Init(void)
{
hi2c3.Instance = I2C3;
hi2c3.Init.Timing = 0x10909CEC;
hi2c3.Init.OwnAddress1 = 0;
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c3.Init.OwnAddress2 = 0;
hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
/**Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* LPUART1 init function */
static void MX_LPUART1_UART_Init(void)
{
hlpuart1.Instance = LPUART1;
hlpuart1.Init.BaudRate = 115200;
hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
hlpuart1.Init.StopBits = UART_STOPBITS_1;
hlpuart1.Init.Parity = UART_PARITY_NONE;
hlpuart1.Init.Mode = UART_MODE_TX_RX;
hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&hlpuart1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* USART2 init function */
static void MX_USART2_UART_Init(void)
{
huart2.Instance = USART2;
huart2.Init.BaudRate = 115200;
huart2.Init.WordLength = UART_WORDLENGTH_8B;
huart2.Init.StopBits = UART_STOPBITS_1;
huart2.Init.Parity = UART_PARITY_NONE;
huart2.Init.Mode = UART_MODE_TX_RX;
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart2) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* USART3 init function */
static void MX_USART3_UART_Init(void)
{
huart3.Instance = USART3;
huart3.Init.BaudRate = 115200;
huart3.Init.WordLength = UART_WORDLENGTH_8B;
huart3.Init.StopBits = UART_STOPBITS_1;
huart3.Init.Parity = UART_PARITY_NONE;
huart3.Init.Mode = UART_MODE_TX_RX;
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart3) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* SAI2 init function */
static void MX_SAI2_Init(void)
{
hsai_BlockA2.Instance = SAI2_Block_A;
hsai_BlockA2.Init.Protocol = SAI_FREE_PROTOCOL;
hsai_BlockA2.Init.AudioMode = SAI_MODEMASTER_TX;
hsai_BlockA2.Init.DataSize = SAI_DATASIZE_24;
hsai_BlockA2.Init.FirstBit = SAI_FIRSTBIT_MSB;
hsai_BlockA2.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
hsai_BlockA2.Init.Synchro = SAI_ASYNCHRONOUS;
hsai_BlockA2.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE;
hsai_BlockA2.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;
hsai_BlockA2.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY;
hsai_BlockA2.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_192K;
hsai_BlockA2.Init.SynchroExt = SAI_SYNCEXT_DISABLE;
hsai_BlockA2.Init.MonoStereoMode = SAI_STEREOMODE;
hsai_BlockA2.Init.CompandingMode = SAI_NOCOMPANDING;
hsai_BlockA2.Init.TriState = SAI_OUTPUT_NOTRELEASED;
hsai_BlockA2.FrameInit.FrameLength = 8;
hsai_BlockA2.FrameInit.ActiveFrameLength = 1;
hsai_BlockA2.FrameInit.FSDefinition = SAI_FS_STARTFRAME;
hsai_BlockA2.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
hsai_BlockA2.FrameInit.FSOffset = SAI_FS_FIRSTBIT;
hsai_BlockA2.SlotInit.FirstBitOffset = 0;
hsai_BlockA2.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE;
hsai_BlockA2.SlotInit.SlotNumber = 1;
hsai_BlockA2.SlotInit.SlotActive = 0x00000000;
if (HAL_SAI_Init(&hsai_BlockA2) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* SDMMC1 init function */
static void MX_SDMMC1_Init(void)
{
}
/* SPI1 init function */
static void MX_SPI1_Init(void)
{
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_1LINE;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi1.Init.CRCPolynomial = 7;
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
if (HAL_SPI_Init(&hspi1) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
}
/* USB_OTG_FS init function */
static void MX_USB_OTG_FS_USB_Init(void)
{
}
/** Configure pins as
* Analog
* Input
* Output
* EVENT_OUT
* EXTI
PC8 ------> SDMMC1_D0
PC9 ------> SDMMC1_D1
PA10 ------> USB_OTG_FS_ID
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
PC10 ------> SDMMC1_D2
PC11 ------> SDMMC1_D3
PC12 ------> SDMMC1_CK
PD2 ------> SDMMC1_CMD
*/
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, AUDIO_CTL_Pin|LCD_PWR_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(PCIE_RST_GPIO_Port, PCIE_RST_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, SECURE_IO_Pin|SECURE_RST_Pin|LCD_DCX_Pin|CAM_MCLK_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, WIFI_RST_Pin|WIFI_WU_Pin|LCD_RST_Pin|USB_PCIE_SW_Pin
|CAM_RST_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, CAM_PD_Pin|AUDIO_RST_Pin|SECURE_CLK_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, HTS_LED_Pin|GS_LED_Pin|ALS_LED_Pin|PS_LED_Pin
|COMPASS_LED_Pin|AUDIO_WU_Pin|ZIGBEE_RST_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(IRDA_CTL_GPIO_Port, IRDA_CTL_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin : SIM_DET_Pin */
GPIO_InitStruct.Pin = SIM_DET_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(SIM_DET_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : AUDIO_CTL_Pin LCD_PWR_Pin CAM_PD_Pin AUDIO_RST_Pin
SECURE_CLK_Pin */
GPIO_InitStruct.Pin = AUDIO_CTL_Pin|LCD_PWR_Pin|CAM_PD_Pin|AUDIO_RST_Pin
|SECURE_CLK_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pin : PCIE_RST_Pin */
GPIO_InitStruct.Pin = PCIE_RST_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(PCIE_RST_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : SECURE_IO_Pin SECURE_RST_Pin LCD_DCX_Pin CAM_MCLK_Pin */
GPIO_InitStruct.Pin = SECURE_IO_Pin|SECURE_RST_Pin|LCD_DCX_Pin|CAM_MCLK_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pins : WIFI_RST_Pin WIFI_WU_Pin LCD_RST_Pin USB_PCIE_SW_Pin
CAM_RST_Pin */
GPIO_InitStruct.Pin = WIFI_RST_Pin|WIFI_WU_Pin|LCD_RST_Pin|USB_PCIE_SW_Pin
|CAM_RST_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : ZIGBEE_INT_Pin KEY_2_Pin KEY_3_Pin KEY_1_Pin */
GPIO_InitStruct.Pin = ZIGBEE_INT_Pin|KEY_2_Pin|KEY_3_Pin|KEY_1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pins : HTS_LED_Pin GS_LED_Pin ALS_LED_Pin PS_LED_Pin
COMPASS_LED_Pin AUDIO_WU_Pin IRDA_CTL_Pin ZIGBEE_RST_Pin */
GPIO_InitStruct.Pin = HTS_LED_Pin|GS_LED_Pin|ALS_LED_Pin|PS_LED_Pin
|COMPASS_LED_Pin|AUDIO_WU_Pin|IRDA_CTL_Pin|ZIGBEE_RST_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pins : PC8 PC9 PC10 PC11
PC12 */
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/*Configure GPIO pins : PA10 PA11 PA12 */
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pin : ALS_INT_Pin */
GPIO_InitStruct.Pin = ALS_INT_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(ALS_INT_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : PD2 */
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pin : IRDA_RX_Pin */
GPIO_InitStruct.Pin = IRDA_RX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(IRDA_RX_GPIO_Port, &GPIO_InitStruct);
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @param file: The file name as string.
* @param line: The line in file as a number.
* @retval None
*/
void _Error_Handler(char *file, int line)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t* file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* File Name : stm32l4xx_hal_msp.c
* Description : This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
extern void _Error_Handler(char *, int);
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* System interrupt init*/
/* MemoryManagement_IRQn interrupt configuration */
HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
/* BusFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
/* UsageFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
/* SVCall_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
/* DebugMonitor_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(hadc->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspInit 0 */
/* USER CODE END ADC3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC_CLK_ENABLE();
/**ADC3 GPIO Configuration
PC2 ------> ADC3_IN3
PC3 ------> ADC3_IN4
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
}
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
{
if(hadc->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspDeInit 0 */
/* USER CODE END ADC3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC_CLK_DISABLE();
/**ADC3 GPIO Configuration
PC2 ------> ADC3_IN3
PC3 ------> ADC3_IN4
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3);
/* USER CODE BEGIN ADC3_MspDeInit 1 */
/* USER CODE END ADC3_MspDeInit 1 */
}
}
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
if(hcrc->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc)
{
if(hcrc->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspDeInit 0 */
/* USER CODE END CRC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_CRC_CLK_DISABLE();
/* USER CODE BEGIN CRC_MspDeInit 1 */
/* USER CODE END CRC_MspDeInit 1 */
}
}
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(hdcmi->Instance==DCMI)
{
/* USER CODE BEGIN DCMI_MspInit 0 */
/* USER CODE END DCMI_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DCMI_CLK_ENABLE();
/**DCMI GPIO Configuration
PE4 ------> DCMI_D4
PE5 ------> DCMI_D6
PE6 ------> DCMI_D7
PD8 ------> DCMI_HSYNC
PD9 ------> DCMI_PIXCLK
PC7 ------> DCMI_D1
PA9 ------> DCMI_D0
PD3 ------> DCMI_D5
PB7 ------> DCMI_VSYNC
PE0 ------> DCMI_D2
PE1 ------> DCMI_D3
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_0
|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF10_DCMI;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF10_DCMI;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF10_DCMI;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF5_DCMI;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF4_DCMI;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF10_DCMI;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN DCMI_MspInit 1 */
/* USER CODE END DCMI_MspInit 1 */
}
}
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
{
if(hdcmi->Instance==DCMI)
{
/* USER CODE BEGIN DCMI_MspDeInit 0 */
/* USER CODE END DCMI_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_DCMI_CLK_DISABLE();
/**DCMI GPIO Configuration
PE4 ------> DCMI_D4
PE5 ------> DCMI_D6
PE6 ------> DCMI_D7
PD8 ------> DCMI_HSYNC
PD9 ------> DCMI_PIXCLK
PC7 ------> DCMI_D1
PA9 ------> DCMI_D0
PD3 ------> DCMI_D5
PB7 ------> DCMI_VSYNC
PE0 ------> DCMI_D2
PE1 ------> DCMI_D3
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_0
|GPIO_PIN_1);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_3);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
/* USER CODE BEGIN DCMI_MspDeInit 1 */
/* USER CODE END DCMI_MspDeInit 1 */
}
}
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(hi2c->Instance==I2C1)
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
else if(hi2c->Instance==I2C2)
{
/* USER CODE BEGIN I2C2_MspInit 0 */
/* USER CODE END I2C2_MspInit 0 */
/**I2C2 GPIO Configuration
PB13 ------> I2C2_SCL
PB14 ------> I2C2_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_I2C2_CLK_ENABLE();
/* USER CODE BEGIN I2C2_MspInit 1 */
/* USER CODE END I2C2_MspInit 1 */
}
else if(hi2c->Instance==I2C3)
{
/* USER CODE BEGIN I2C3_MspInit 0 */
/* USER CODE END I2C3_MspInit 0 */
/**I2C3 GPIO Configuration
PC0 ------> I2C3_SCL
PC1 ------> I2C3_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_I2C3_CLK_ENABLE();
/* USER CODE BEGIN I2C3_MspInit 1 */
/* USER CODE END I2C3_MspInit 1 */
}
}
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
{
if(hi2c->Instance==I2C1)
{
/* USER CODE BEGIN I2C1_MspDeInit 0 */
/* USER CODE END I2C1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C1_CLK_DISABLE();
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_9);
/* USER CODE BEGIN I2C1_MspDeInit 1 */
/* USER CODE END I2C1_MspDeInit 1 */
}
else if(hi2c->Instance==I2C2)
{
/* USER CODE BEGIN I2C2_MspDeInit 0 */
/* USER CODE END I2C2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C2_CLK_DISABLE();
/**I2C2 GPIO Configuration
PB13 ------> I2C2_SCL
PB14 ------> I2C2_SDA
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14);
/* USER CODE BEGIN I2C2_MspDeInit 1 */
/* USER CODE END I2C2_MspDeInit 1 */
}
else if(hi2c->Instance==I2C3)
{
/* USER CODE BEGIN I2C3_MspDeInit 0 */
/* USER CODE END I2C3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C3_CLK_DISABLE();
/**I2C3 GPIO Configuration
PC0 ------> I2C3_SCL
PC1 ------> I2C3_SDA
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1);
/* USER CODE BEGIN I2C3_MspDeInit 1 */
/* USER CODE END I2C3_MspDeInit 1 */
}
}
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(huart->Instance==LPUART1)
{
/* USER CODE BEGIN LPUART1_MspInit 0 */
/* USER CODE END LPUART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LPUART1_CLK_ENABLE();
/**LPUART1 GPIO Configuration
PB10 ------> LPUART1_RX
PB11 ------> LPUART1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* LPUART1 interrupt Init */
HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(LPUART1_IRQn);
/* USER CODE BEGIN LPUART1_MspInit 1 */
/* USER CODE END LPUART1_MspInit 1 */
}
else if(huart->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
else if(huart->Instance==USART3)
{
/* USER CODE BEGIN USART3_MspInit 0 */
/* USER CODE END USART3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART3_CLK_ENABLE();
/**USART3 GPIO Configuration
PC4 ------> USART3_TX
PC5 ------> USART3_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* USART3 interrupt Init */
HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspInit 1 */
/* USER CODE END USART3_MspInit 1 */
}
}
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==LPUART1)
{
/* USER CODE BEGIN LPUART1_MspDeInit 0 */
/* USER CODE END LPUART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_LPUART1_CLK_DISABLE();
/**LPUART1 GPIO Configuration
PB10 ------> LPUART1_RX
PB11 ------> LPUART1_TX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11);
/* LPUART1 interrupt DeInit */
HAL_NVIC_DisableIRQ(LPUART1_IRQn);
/* USER CODE BEGIN LPUART1_MspDeInit 1 */
/* USER CODE END LPUART1_MspDeInit 1 */
}
else if(huart->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspDeInit 0 */
/* USER CODE END USART2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART2_CLK_DISABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
/* USART2 interrupt DeInit */
HAL_NVIC_DisableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspDeInit 1 */
/* USER CODE END USART2_MspDeInit 1 */
}
else if(huart->Instance==USART3)
{
/* USER CODE BEGIN USART3_MspDeInit 0 */
/* USER CODE END USART3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART3_CLK_DISABLE();
/**USART3 GPIO Configuration
PC4 ------> USART3_TX
PC5 ------> USART3_RX
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5);
/* USART3 interrupt DeInit */
HAL_NVIC_DisableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspDeInit 1 */
/* USER CODE END USART3_MspDeInit 1 */
}
}
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(hspi->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
/**SPI1 GPIO Configuration
PA4 ------> SPI1_NSS
PA5 ------> SPI1_SCK
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
{
if(hspi->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspDeInit 0 */
/* USER CODE END SPI1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI1_CLK_DISABLE();
/**SPI1 GPIO Configuration
PA4 ------> SPI1_NSS
PA5 ------> SPI1_SCK
PA7 ------> SPI1_MOSI
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_7);
/* USER CODE BEGIN SPI1_MspDeInit 1 */
/* USER CODE END SPI1_MspDeInit 1 */
}
}
static uint32_t SAI2_client =0;
void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* SAI2 */
if(hsai->Instance==SAI2_Block_A)
{
/* Peripheral clock enable */
if (SAI2_client == 0)
{
__HAL_RCC_SAI2_CLK_ENABLE();
}
SAI2_client ++;
/**SAI2_A_Block_A GPIO Configuration
PB12 ------> SAI2_FS_A
PB15 ------> SAI2_SD_A
PD10 ------> SAI2_SCK_A
PC6 ------> SAI2_MCLK_A
*/
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF13_SAI2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF13_SAI2;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF13_SAI2;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
}
}
void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai)
{
/* SAI2 */
if(hsai->Instance==SAI2_Block_A)
{
SAI2_client --;
if (SAI2_client == 0)
{
/* Peripheral clock disable */
__HAL_RCC_SAI2_CLK_DISABLE();
}
/**SAI2_A_Block_A GPIO Configuration
PB12 ------> SAI2_FS_A
PB15 ------> SAI2_SD_A
PD10 ------> SAI2_SCK_A
PC6 ------> SAI2_MCLK_A
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6);
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32l4xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#include "stm32l4xx.h"
#include "stm32l4xx_it.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern UART_HandleTypeDef hlpuart1;
extern UART_HandleTypeDef huart2;
extern UART_HandleTypeDef huart3;
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
/* USER CODE BEGIN HardFault_IRQn 1 */
/* USER CODE END HardFault_IRQn 1 */
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
/* USER CODE BEGIN MemoryManagement_IRQn 1 */
/* USER CODE END MemoryManagement_IRQn 1 */
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
/* USER CODE BEGIN BusFault_IRQn 1 */
/* USER CODE END BusFault_IRQn 1 */
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
/* USER CODE BEGIN UsageFault_IRQn 1 */
/* USER CODE END UsageFault_IRQn 1 */
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
HAL_SYSTICK_IRQHandler();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32L4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32l4xx.s). */
/******************************************************************************/
/**
* @brief This function handles EXTI line[9:5] interrupts.
*/
void EXTI9_5_IRQHandler(void)
{
/* USER CODE BEGIN EXTI9_5_IRQn 0 */
/* USER CODE END EXTI9_5_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
/* USER CODE BEGIN EXTI9_5_IRQn 1 */
/* USER CODE END EXTI9_5_IRQn 1 */
}
/**
* @brief This function handles USART2 global interrupt.
*/
void USART2_IRQHandler(void)
{
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
/**
* @brief This function handles USART3 global interrupt.
*/
void USART3_IRQHandler(void)
{
/* USER CODE BEGIN USART3_IRQn 0 */
/* USER CODE END USART3_IRQn 0 */
HAL_UART_IRQHandler(&huart3);
/* USER CODE BEGIN USART3_IRQn 1 */
/* USER CODE END USART3_IRQn 1 */
}
/**
* @brief This function handles EXTI line[15:10] interrupts.
*/
void EXTI15_10_IRQHandler(void)
{
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 1 */
}
/**
* @brief This function handles LPUART1 global interrupt.
*/
void LPUART1_IRQHandler(void)
{
/* USER CODE BEGIN LPUART1_IRQn 0 */
/* USER CODE END LPUART1_IRQn 0 */
HAL_UART_IRQHandler(&hlpuart1);
/* USER CODE BEGIN LPUART1_IRQn 1 */
/* USER CODE END LPUART1_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the MSI (4 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | MSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/** @addtogroup STM32L4xx_System_Private_Includes
* @{
*/
#include "stm32l4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 4000000U;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC->CR |= RCC_CR_MSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000U;
/* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC->CR &= 0xEAF6FFFFU;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00001000U;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
/* Get MSI Range frequency--------------------------------------------------*/
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
{ /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case 0x00: /* MSI used as system clock source */
SystemCoreClock = msirange;
break;
case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
switch (pllsource)
{
case 0x02: /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm);
break;
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
break;
default: /* MSI used as PLL clock source */
pllvco = (msirange / pllm);
break;
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
SystemCoreClock = pllvco/pllr;
break;
default:
SystemCoreClock = msirange;
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

11
Living_SDK/board/developerkit/aos/atcmd_config_platform.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef _ATCMD_CONFIG_PLATFORM_H_
#define _ATCMD_CONFIG_PLATFORM_H_
// AT uart
#define AT_UART_PORT 3
#endif

40
Living_SDK/board/developerkit/aos/board.c Normal file
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#include "hal/soc/soc.h"
#include <aos/kernel.h>
/* Logic partition on flash devices */
hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX];
static void board_partition_init()
{
hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_APPLICATION].partition_description = "Application";
hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = 0x08000000;
hal_partitions[HAL_PARTITION_APPLICATION].partition_length = 0x3C000; //240k bytes
hal_partitions[HAL_PARTITION_APPLICATION].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = "PARAMETER1";
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = 0x0803C000;
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = 0x1000; // 4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = "PARAMETER2";
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = 0x0803D000;
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = 0x2000; //8k bytes
hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_owner = HAL_FLASH_EMBEDDED;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_description = "PARAMETER4";
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_start_addr = 0x0803F000;
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_length = 0x1000; //4k bytes
hal_partitions[HAL_PARTITION_PARAMETER_4].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
}
void board_init(void)
{
board_partition_init();
board_cli_init();
}

10
Living_SDK/board/developerkit/aos/board.h Normal file
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#define HARDWARE_REVISION "V1.0"
#define MODEL "STM32L4"
#ifdef BOOTLOADER
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#else
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#endif

217
Living_SDK/board/developerkit/aos/board_cli.c Normal file
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#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <aos/aos.h>
#include <atparser.h>
#define STARTERKIT_WIFI_MODULE_FOTA "AT+FOTA"
#define FOTA_OOB_PREFIX "+FOTAEVENT:"
#define FOTA_OOB_POSTFIX "\r\n"
typedef struct modulefotastatus {
int ret;
aos_sem_t stmoduelfotasem;
} fotastatus_t;
static fotastatus_t fota_status;
static int module_fota_firmware_size_check(char *pcsize)
{
int i = 0;
if (NULL == pcsize){
printf("invalid input at $s %d \r\n", __FILE__, __LINE__);
return -1;
}
/*It's impossible that the size of firmware can over 10e9*/
if (strlen(pcsize) > 10) {
printf("invalid lenth %s at %s %d \r\n ", pcsize, __FILE__, __LINE__);
return -1;
}
for (i = 0; i < strlen(pcsize); i++){
if (pcsize[i] < '0' || pcsize[i] > '9'){
printf("invalid lenth %s at %s %d \r\n ", pcsize, __FILE__, __LINE__);
return -1;
}
}
return 0;
}
static int module_fota_firmware_md5_check(char *pcmd5)
{
int i = 0;
if (NULL == pcmd5){
printf("invalid input at $s %d \r\n", __FILE__, __LINE__);
return -1;
}
/*It's impossible that the length of md5 value can over 64*/
if (strlen(pcmd5) > 64) {
printf("invalid lenth %s at %s %d \r\n ", pcmd5, __FILE__, __LINE__);
return -1;
}
for (i = 0; i < strlen(pcmd5); i++){
if (!((pcmd5[i] >= '0' && pcmd5[i] <= '9')
|| (pcmd5[i] >= 'a' && pcmd5[i] <= 'f')
|| (pcmd5[i] >= 'A' && pcmd5[i] <= 'F'))){
printf("invalid lenth %s at %s %d \r\n ", pcmd5, __FILE__, __LINE__);
return -1;
}
}
return 0;
}
static int wifi_module_fota(char *pcsize, char *pcversion, char *pcurl, char *pcmd5)
{
char *pcatcmd = NULL;
char out[64] = {0};
int cmdlen = 0;
int ret = 0;
if (NULL == pcsize || NULL == pcversion || NULL == pcurl || NULL == pcmd5){
printf("invalid input at %s %d \r\n", __FILE__, __LINE__);
return -1;
}
pcatcmd = aos_malloc(1024);
if (NULL == pcatcmd){
printf("fail to malloc memory at %s %d \r\n", __FILE__, __LINE__);
return -1;
}
memset(pcatcmd, 0, 1024);
cmdlen = snprintf(pcatcmd, 1024, "%s=%s,%s,%s,%s", STARTERKIT_WIFI_MODULE_FOTA, pcsize,
pcversion, pcurl, pcmd5);
if (cmdlen >= 1024){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
ret = -1;
goto end;
}
ret = at.send_raw(pcatcmd, out, sizeof(out));
LOGD(TAG, "The AT response is: %s", out);
if (strstr(out, AT_RECV_FAIL_POSTFIX) != NULL || ret != 0) {
printf("%s %d failed", __func__, __LINE__);
ret = -1;
goto end;
}
aos_sem_wait(&fota_status.stmoduelfotasem , AOS_WAIT_FOREVER);
if (fota_status.ret != 0){
printf("module fota failed at %s %d \r\n", __FILE__, __LINE__);
ret = -1;
}
end:
aos_free(pcatcmd);
return ret;
}
static void handle_module_fota_cmd(char *pwbuf, int blen, int argc, char **argv)
{
int ret = 0;
char *pcsize = NULL;
char *pcversion = NULL;
char *pcurl = NULL;
char *pcmd5 = NULL;
if (argc != 5 || NULL == argv){
aos_cli_printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
pcsize = argv[1];
/*or check if atoi(pcsize) <= 0, is invalid*/
if (module_fota_firmware_size_check(pcsize) != 0){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
pcversion = argv[2];
if (strlen(pcversion) >= 64){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
pcurl = argv[3];
if (strlen(pcversion) >= 512){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
pcmd5 = argv[4];
if (module_fota_firmware_md5_check(pcmd5) != 0){
printf("invalid cmd at %s %d \r\n", __FILE__, __LINE__);
return;
}
printf("It's going to start wifi module fota it will cost several minutes. Please be patient, and Do not power off the module or reboot befor ota is finished. \r\n");
ret = wifi_module_fota(pcsize, pcversion, pcurl, pcmd5);
if (ret != 0){
printf("module-ota excute failed \r\n");
}else{
printf("module-ota excute successed \r\n");
}
return;
}
struct cli_command module_ota_cli_cmd[] = {
{
.name = "module-ota",
.help = "module-ota size version url md5-value",
.function = handle_module_fota_cmd
}
};
void fota_event_handler(void *arg, char *buf, int buflen)
{
int ret = -1;
if (NULL == buf || 0 == buflen){
printf("invalid input %s %d \r\n", __FILE__, __LINE__);
goto end;
}
if (strstr(buf, AT_RECV_FAIL_POSTFIX) != NULL){
printf("module-fota result is %s \r\n", buf);
goto end;
}
ret = 0;
end:
fota_status.ret = ret;
aos_sem_signal(&fota_status.stmoduelfotasem);
}
static void wifi_event_handler(input_event_t *event, void *priv_data)
{
if (event->type != EV_WIFI)
return;
if (event->code == CODE_WIFI_ON_GOT_IP){
at.oob(FOTA_OOB_PREFIX, FOTA_OOB_POSTFIX, 64, fota_event_handler, NULL);
aos_cli_register_commands(&module_ota_cli_cmd[0],sizeof(module_ota_cli_cmd) / sizeof(struct cli_command));
LOG("Hello, WiFi GOT_IP event! at %s %d\r\n", __FILE__, __LINE__);
}
}
int board_cli_init(void)
{
int ret = 0;
ret = aos_sem_new(&fota_status.stmoduelfotasem, 0);
if (ret){
printf("fail to creat sem4 %s %d \r\n", __FILE__, __LINE__);
}
fota_status.ret = 0;
aos_register_event_filter(EV_WIFI, wifi_event_handler, NULL);
}

229
Living_SDK/board/developerkit/aos/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 0
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 100
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#ifndef RHINO_CONFIG_SYSTEM_STACK_SIZE
#define RHINO_CONFIG_SYSTEM_STACK_SIZE 0x400
#endif
#endif /* CONFIG_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <stdint.h>
#include "hal/hal.h"
#include "k_config.h"
#include "soc_init.h"
#define main st_main
#include "Src/main.c"
#if defined (__CC_ARM) && defined(__MICROLIB)
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#define GETCHAR_PROTOTYPE int fgetc(FILE *f)
size_t g_iram1_start = 0x20000000;
size_t g_iram1_total_size = 0x00040000;
#elif defined(__ICCARM__)
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#define GETCHAR_PROTOTYPE int fgetc(FILE *f)
#else
/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
set to 'Yes') calls __io_putchar() */
#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
#define GETCHAR_PROTOTYPE int __io_getchar(void)
#endif /* defined (__CC_ARM) && defined(__MICROLIB) */
uart_dev_t uart_0;
static void stduart_init(void);
static void brd_peri_init(void);
static void MX_SPI1_Init(void);
static void MX_SAI1_Init(void);
static void MX_CRC_Init(void);
static void MX_DMA_Init(void);
void stm32_soc_init(void)
{
HAL_Init();
/* Configure the system clock */
SystemClock_Config();
/**Configure the Systick interrupt time
*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/RHINO_CONFIG_TICKS_PER_SECOND);
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 0x0f, 0);
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*default uart init*/
stduart_init();
//brd_peri_init();
//MX_DMA_Init();
//MX_SAI1_Init();
//MX_SPI1_Init();
//MX_CRC_Init();
}
static void stduart_init(void)
{
uart_0.port = STDIO_UART;
uart_0.config.baud_rate = 115200;
uart_0.config.data_width = DATA_WIDTH_8BIT;
uart_0.config.flow_control = FLOW_CONTROL_DISABLED;
uart_0.config.mode = MODE_TX_RX;
uart_0.config.parity = NO_PARITY;
uart_0.config.stop_bits = STOP_BITS_1;
hal_uart_init(&uart_0);
}
static gpio_irq_trigger_t mode_rising = IRQ_TRIGGER_RISING_EDGE;
static gpio_irq_trigger_t mode_falling = IRQ_TRIGGER_FALLING_EDGE;
static gpio_irq_trigger_t mode_both = IRQ_TRIGGER_BOTH_EDGES;
static uint8_t gpio_set = 1;
static uint8_t gpio_reset = 0;
gpio_dev_t brd_gpio_table[] = {
{ALS_INT, IRQ_MODE, &mode_rising}, //PB8
{AUDIO_EN, OUTPUT_PUSH_PULL, &gpio_set}, //PA8
{LCD_DCX, OUTPUT_PUSH_PULL, &gpio_reset}, //PB1
{LCD_PWR, OUTPUT_PUSH_PULL, &gpio_reset}, //PA0
{LCD_RST, OUTPUT_PUSH_PULL, &gpio_set}, //PA1
{LED_ALS, OUTPUT_PUSH_PULL, &gpio_set}, //PB5
{LED_GS, OUTPUT_PUSH_PULL, &gpio_set}, //PB2
{LED_HTS, OUTPUT_PUSH_PULL, &gpio_set}, //PA15
{LED_PS, OUTPUT_PUSH_PULL, &gpio_set}, //PA12
{SW_FUNC_A, IRQ_MODE, &mode_rising}, //PA11
{SW_FUNC_B, IRQ_MODE, &mode_rising}, //PC13
{SW_WIFI, IRQ_MODE, &mode_rising}, //PB0
{WIFI_RST, OUTPUT_PUSH_PULL, &gpio_set}, //PB4
{WIFI_WU, OUTPUT_PUSH_PULL, &gpio_set}, //PB9
};
i2c_dev_t brd_i2c1_dev = {AOS_PORT_I2C1, {0}, NULL};
i2c_dev_t brd_i2c2_dev = {AOS_PORT_I2C2, {0}, NULL};
static void brd_peri_init(void)
{
int i;
int gpcfg_num = sizeof(brd_gpio_table) / sizeof(brd_gpio_table[0]);
for (i = 0; i < gpcfg_num; ++i) {
hal_gpio_init(&brd_gpio_table[i]);
}
hal_i2c_init(&brd_i2c1_dev);
hal_i2c_init(&brd_i2c2_dev);
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
HAL_IncTick();
krhino_intrpt_enter();
krhino_tick_proc();
krhino_intrpt_exit();
}
void HardFault_Handler(void)
{
while (1)
{
//#ifdef exc_print
// cpu_hardfault_handle();
// #endif
}
}
/**
* @brief Retargets the C library printf function to the USART.
* @param None
* @retval None
*/
PUTCHAR_PROTOTYPE
{
if (ch == '\n') {
//hal_uart_send(&console_uart, (void *)"\r", 1, 30000);
hal_uart_send(&uart_0, (void *)"\r", 1, 30000);
}
hal_uart_send(&uart_0, &ch, 1, 30000);
return ch;
}
/**
* @brief Retargets the C library scanf function to the USART.
* @param None
* @retval None
*/
GETCHAR_PROTOTYPE
{
/* Place your implementation of fgetc here */
/* e.g. readwrite a character to the USART2 and Loop until the end of transmission */
uint8_t ch = EOF;
int32_t ret = -1;
uint32_t recv_size;
ret = hal_uart_recv_II(&uart_0, &ch, 1, &recv_size, HAL_WAIT_FOREVER);
if (ret == 0) {
return ch;
} else {
return -1;
}
}

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/**
******************************************************************************
* File Name : main.hpp
* Description : This file contains the common defines of the application
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SOC_INIT_H
#define __SOC_INIT_H
/* Includes ------------------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "hal/hal.h"
#include "hal/hal_gpio_stm32l4.h"
#include "hal/hal_i2c_stm32l4.h"
#include "hal/hal_uart_stm32l4.h"
/* USER CODE END Includes */
/* Private define ------------------------------------------------------------*/
typedef enum {
GPIO_ALS_INT,
GPIO_AUDIO_EN,
GPIO_LCD_DCX,
GPIO_LCD_PWR,
GPIO_LCD_RST,
GPIO_LED_ALS,
GPIO_LED_GS,
GPIO_LED_HTS,
GPIO_LED_PS,
GPIO_SW_FUNC_A,
GPIO_SW_FUNC_B,
GPIO_SW_WIFI,
GPIO_WIFI_RST,
GPIO_WIFI_WU,
MAX_GPIO_NUM
} BOARD_GPIO;
extern gpio_dev_t brd_gpio_table[];
extern i2c_dev_t brd_i2c1_dev;
extern i2c_dev_t brd_i2c2_dev;
extern uart_dev_t brd_uart1_dev;
/* legency definition for the modules have no hal layer */
#define SW_FUNC_B_Pin GPIO_PIN_13
#define SW_FUNC_B_GPIO_Port GPIOC
#define SW_FUNC_B_EXTI_IRQn EXTI15_10_IRQn
#define LCD_PWR_Pin GPIO_PIN_0
#define LCD_PWR_GPIO_Port GPIOA
#define LCD_RST_Pin GPIO_PIN_1
#define LCD_RST_GPIO_Port GPIOA
#define LCD_NSS_Pin GPIO_PIN_4
#define LCD_NSS_GPIO_Port GPIOA
#define LCD_SCK_Pin GPIO_PIN_5
#define LCD_SCK_GPIO_Port GPIOA
#define LCD_TX_Pin GPIO_PIN_7
#define LCD_TX_GPIO_Port GPIOA
#define SW_WIFI_Pin GPIO_PIN_0
#define SW_WIFI_GPIO_Port GPIOB
#define SW_WIFI_EXTI_IRQn EXTI0_IRQn
#define LCD_DCX_Pin GPIO_PIN_1
#define LCD_DCX_GPIO_Port GPIOB
#define LED_GS_Pin GPIO_PIN_2
#define LED_GS_GPIO_Port GPIOB
#define AUDIO_EN_Pin GPIO_PIN_8
#define AUDIO_EN_GPIO_Port GPIOA
#define SW_FUNC_A_Pin GPIO_PIN_11
#define SW_FUNC_A_GPIO_Port GPIOA
#define SW_FUNC_A_EXTI_IRQn EXTI15_10_IRQn
#define LED_PS_Pin GPIO_PIN_12
#define LED_PS_GPIO_Port GPIOA
#define LED_HTS_Pin GPIO_PIN_15
#define LED_HTS_GPIO_Port GPIOA
#define WIFI_RST_Pin GPIO_PIN_4
#define WIFI_RST_GPIO_Port GPIOB
#define LED_ALS_Pin GPIO_PIN_5
#define LED_ALS_GPIO_Port GPIOB
#define WIFI_TX_Pin GPIO_PIN_6
#define WIFI_TX_GPIO_Port GPIOB
#define WIFI_RX_Pin GPIO_PIN_7
#define WIFI_RX_GPIO_Port GPIOB
#define ALS_INT_Pin GPIO_PIN_8
#define ALS_INT_GPIO_Port GPIOB
#define ALS_INT_EXTI_IRQn EXTI9_5_IRQn
#define WIFI_WU_Pin GPIO_PIN_9
#define WIFI_WU_GPIO_Port GPIOB
#define B1_Pin GPIO_PIN_13
#define B1_GPIO_Port GPIOC
#define MCO_Pin GPIO_PIN_0
#define MCO_GPIO_Port GPIOH
#define USART_RX_Pin GPIO_PIN_3
#define USART_RX_GPIO_Port GPIOA
#define LD4_Pin GPIO_PIN_5
#define LD4_GPIO_Port GPIOA
#define SMPS_EN_Pin GPIO_PIN_12
#define SMPS_EN_GPIO_Port GPIOB
#define SMPS_V1_Pin GPIO_PIN_13
#define SMPS_V1_GPIO_Port GPIOB
#define SMPS_PG_Pin GPIO_PIN_14
#define SMPS_PG_GPIO_Port GPIOB
#define SPMS_SW_Pin GPIO_PIN_15
#define SPMS_SW_GPIO_Port GPIOB
#define TMS_Pin GPIO_PIN_13
#define TMS_GPIO_Port GPIOA
#define TCK_Pin GPIO_PIN_14
#define TCK_GPIO_Port GPIOA
#define SWO_Pin GPIO_PIN_3
#define SWO_GPIO_Port GPIOB
#define LCD_DCX_Pin GPIO_PIN_1
#define LCD_DCX_GPIO_Port GPIOB
#define LCD_PWR_Pin GPIO_PIN_0
#define LCD_PWR_GPIO_Port GPIOA
#define LCD_RST_Pin GPIO_PIN_1
#define LCD_RST_GPIO_Port GPIOA
#define LCD_NSS_Pin GPIO_PIN_4
#define LCD_NSS_GPIO_Port GPIOA
#define LCD_SCK_Pin GPIO_PIN_5
#define LCD_SCK_GPIO_Port GPIOA
#define LCD_TX_Pin GPIO_PIN_7
#define LCD_TX_GPIO_Port GPIOA
#define KIDS_A10_PRT(fmt, args...) \
printf("%s: [%s-->%d]=> "fmt, \
__FILE__, __FUNCTION__, \
__LINE__, ##args)
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
extern "C" {
#endif
void _Error_Handler(char *, int);
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* __SOC_INIT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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#include <stdlib.h>
#include <string.h>
#include "stm32l4xx_hal.h"
#include "soc_init.h"
#include "st7789.h"
extern SPI_HandleTypeDef hspi1;
static SPI_HandleTypeDef *hspi_lcd = NULL;
static struct st7789_function st7789_cfg_script[] = {
{ST7789_START, ST7789_START},
{ST7789_CMD, 0x11},
{ST7789_DELAY, 120},
{ST7789_CMD, 0x36},
{ST7789_DATA, 0x00},
{ST7789_CMD, 0x3a},
{ST7789_DATA, 0x05},
{ST7789_CMD, 0xb2},
{ST7789_DATA, 0x0c},
{ST7789_DATA, 0x0c},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x33},
{ST7789_DATA, 0x33},
{ST7789_CMD, 0xb7},
{ST7789_DATA, 0x72},
{ST7789_CMD, 0xbb},
{ST7789_DATA, 0x3d},
{ST7789_CMD, 0xc2},
{ST7789_DATA, 0x01},
{ST7789_CMD, 0xc3},
{ST7789_DATA, 0x19},
{ST7789_CMD, 0xc4},
{ST7789_DATA, 0x20},
{ST7789_CMD, 0xc6},
{ST7789_DATA, 0x0f},
{ST7789_CMD, 0xd0},
{ST7789_DATA, 0xa4},
{ST7789_DATA, 0xa1},
{ST7789_CMD, 0xe0},
{ST7789_DATA, 0x70},
{ST7789_DATA, 0x04},
{ST7789_DATA, 0x08},
{ST7789_DATA, 0x09},
{ST7789_DATA, 0x09},
{ST7789_DATA, 0x05},
{ST7789_DATA, 0x2a},
{ST7789_DATA, 0x33},
{ST7789_DATA, 0x41},
{ST7789_DATA, 0x07},
{ST7789_DATA, 0x13},
{ST7789_DATA, 0x13},
{ST7789_DATA, 0x29},
{ST7789_DATA, 0x2f},
{ST7789_CMD, 0xe1},
{ST7789_DATA, 0x70},
{ST7789_DATA, 0x03},
{ST7789_DATA, 0x09},
{ST7789_DATA, 0x0a},
{ST7789_DATA, 0x09},
{ST7789_DATA, 0x06},
{ST7789_DATA, 0x2b},
{ST7789_DATA, 0x34},
{ST7789_DATA, 0x41},
{ST7789_DATA, 0x07},
{ST7789_DATA, 0x12},
{ST7789_DATA, 0x14},
{ST7789_DATA, 0x28},
{ST7789_DATA, 0x2e},
{ST7789_CMD, 0x21},
{ST7789_CMD, 0x29},
{ST7789_CMD, 0x2a},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0xef},
{ST7789_CMD, 0x2b},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0x00},
{ST7789_DATA, 0xef},
{ST7789_CMD, 0x2c},
{ST7789_END, ST7789_END},
};
static HAL_StatusTypeDef st7789_write(int is_cmd, uint8_t data)
{
uint8_t pData[2] = {0};
if (hspi_lcd == NULL) {
_Error_Handler(__FILE__, __LINE__);
return HAL_ERROR;
}
pData[0] = data;
#ifdef ALIOS_HAL
if (is_cmd)
hal_gpio_output_low(&brd_gpio_table[GPIO_LCD_DCX]);
else
hal_gpio_output_high(&brd_gpio_table[GPIO_LCD_DCX]);
#else
if (is_cmd)
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_RESET);
else
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_SET);
#endif
return HAL_SPI_Transmit(hspi_lcd, pData, 1, HAL_MAX_DELAY);
}
static HAL_StatusTypeDef st7789_write_fb(uint16_t *data, uint16_t size)
{
if (hspi_lcd == NULL) {
_Error_Handler(__FILE__, __LINE__);
return HAL_ERROR;
}
return HAL_SPI_Transmit(hspi_lcd, (uint8_t *)data, size, HAL_MAX_DELAY);
}
static void st7789_run_cfg_script()
{
uint8_t data[2] = {0};
int i = 0;
int end_script = 0;
do {
switch (st7789_cfg_script[i].cmd) {
case ST7789_START:
break;
case ST7789_CMD:
data[0] = st7789_cfg_script[i].data & 0xff;
st7789_write(1, data[0]);
break;
case ST7789_DATA:
data[0] = st7789_cfg_script[i].data & 0xff;
st7789_write(0, data[0]);
break;
case ST7789_DELAY:
krhino_task_sleep(krhino_ms_to_ticks(st7789_cfg_script[i].data));
break;
case ST7789_END:
end_script = 1;
}
i++;
} while (!end_script);
}
static void st7789_reset()
{
#ifdef ALIOS_HAL
hal_gpio_output_high(&brd_gpio_table[GPIO_LCD_PWR]);
hal_gpio_output_high(&brd_gpio_table[GPIO_LCD_RST]);
krhino_task_sleep(krhino_ms_to_ticks(50));
hal_gpio_output_low(&brd_gpio_table[GPIO_LCD_RST]);
krhino_task_sleep(krhino_ms_to_ticks(50));
hal_gpio_output_high(&brd_gpio_table[GPIO_LCD_RST]);
krhino_task_sleep(krhino_ms_to_ticks(150));
#else
HAL_GPIO_WritePin(LCD_PWR_GPIO_Port, LCD_PWR_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_SET);
HAL_Delay(50);
/* Reset controller */
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_RESET);
HAL_Delay(50);
HAL_GPIO_WritePin(LCD_RST_GPIO_Port, LCD_RST_Pin, GPIO_PIN_SET);
HAL_Delay(150);
#endif
}
#if 0
static void st7789_set_addr_win(uint16_t xs, uint16_t ys, uint16_t xe, uint16_t ye)
{
uint8_t col_data[4] = {0};
uint8_t row_data[4] = {0};
col_data[0] = xs >> 8 & 0xff;
col_data[1] = xs & 0xff;
col_data[2] = xe >> 8 & 0xff;
col_data[3] = xe & 0xff;
row_data[0] = ys >> 8 & 0xff;
row_data[1] = ys & 0xff;
row_data[2] = ye >> 8 & 0xff;
row_data[3] = ye & 0xff;
st7789_write(1, ST7789_CASET);
st7789_write(0, col_data[0]);
st7789_write(0, col_data[1]);
st7789_write(0, col_data[2]);
st7789_write(0, col_data[3]);
st7789_write(1, ST7789_RASET);
st7789_write(0, row_data[0]);
st7789_write(0, row_data[1]);
st7789_write(0, row_data[2]);
st7789_write(0, row_data[3]);
}
#define LCD_MAX_MEM16_BLOCK (1 << 6)
#define LCD_PIXEL_PER_BLOCK (LCD_MAX_MEM16_BLOCK >> 1)
static void spec_send_fb(uint16_t color, uint16_t pixel_num)
{
int i;
int count, remain;
uint16_t real_mem[LCD_MAX_MEM16_BLOCK] = {0};
for (i = 0; i < LCD_MAX_MEM16_BLOCK; ++i) {
real_mem[i] = color;
}
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_SET);
if (pixel_num <= LCD_MAX_MEM16_BLOCK) {
st7789_write_fb(real_mem, pixel_num << 1);
} else {
count = pixel_num / LCD_MAX_MEM16_BLOCK;
remain = pixel_num % LCD_MAX_MEM16_BLOCK;
for (i = 0; i < count; ++i) {
st7789_write_fb(real_mem, LCD_MAX_MEM16_BLOCK << 1);
}
st7789_write_fb(real_mem, remain << 1);
}
}
static void st7789_display_picture(void)
{
st7789_write(1, ST7789_RAMWR);
spec_send_fb(0x0, WIDTH * HEIGHT / 4);
spec_send_fb(0x1111, WIDTH * HEIGHT / 4);
spec_send_fb(0x7777, WIDTH * HEIGHT / 4);
spec_send_fb(0xeeee, WIDTH * HEIGHT / 4);
}
#endif
int st7789_init()
{
hspi_lcd = &hspi1;
st7789_reset();
st7789_run_cfg_script();
// st7789_display_picture();
return HAL_OK;
}
void ST7789H2_WriteReg(uint8_t Command, uint8_t *Parameters, uint8_t NbParameters)
{
uint8_t i;
/* Send command */
LcdWriteReg(Command);
/* Send command's parameters if any */
for (i=0; i<NbParameters; i++)
{
LcdWriteData(Parameters[i]);
}
}
void ST7789H2_SetCursor(uint16_t Xpos, uint16_t Ypos)
{
uint8_t parameter[4];
/* CASET: Comumn Addrses Set */
parameter[0] = 0x00;
parameter[1] = 0x00 + Xpos;
parameter[2] = 0x00;
parameter[3] = 0xEF + Xpos;
ST7789H2_WriteReg(0x2A, parameter, 4);
/* RASET: Row Addrses Set */
parameter[0] = 0x00;
parameter[1] = 0x00 + Ypos;
parameter[2] = 0x00;
parameter[3] = 0xEF + Ypos;
ST7789H2_WriteReg(0x2B, parameter, 4);
}
uint8_t black_gui[480] = {0};
void BSP_LCD_Clear(uint16_t Color)
{
uint32_t counter = 0;
uint32_t y_size = 0;
memset(black_gui, 0xFF, sizeof(black_gui));
for (counter = 0; counter < 240; counter++)
{
/* Set Cursor */
ST7789H2_SetCursor(0, counter);
/* Prepare to write to LCD RAM */
ST7789H2_WriteReg(0x2C, (uint8_t*)NULL, 0); /* RAM write data command */
LcdWriteDataMultiple(black_gui, 480);
}
}
void ST7789H2_WritePixel(uint16_t Xpos, uint16_t Ypos, uint16_t RGBCode)
{
/* Set Cursor */
ST7789H2_SetCursor(Xpos, Ypos);
/* Prepare to write to LCD RAM */
ST7789H2_WriteReg(0x2C, (uint8_t*)NULL, 0); /* RAM write data command */
/* Write RAM data */
LcdWriteDataMultiple(&RGBCode, 2);
}
void LcdWriteReg(uint8_t Data)
{
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi1, &Data, 1, 10);
}
void LcdWriteData(uint8_t Data)
{
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_SET);
HAL_SPI_Transmit(&hspi1, &Data, 1, 10);
}
void LcdWriteDataMultiple(uint8_t * pData, int NumItems)
{
HAL_GPIO_WritePin(LCD_DCX_GPIO_Port, LCD_DCX_Pin, GPIO_PIN_SET);
HAL_SPI_Transmit(&hspi1, pData, NumItems, 10);
}

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#ifndef __ST7789_H
#define __ST7789_H
#define WIDTH 240
#define HEIGHT 240
#define BPP 16
/* Init script function */
struct st7789_function {
uint8_t cmd;
uint16_t data;
};
/* Init script commands */
enum st7789_cmd {
ST7789_START,
ST7789_END,
ST7789_CMD,
ST7789_DATA,
ST7789_DELAY
};
/* ST7789 Commands */
#define ST7789_CASET 0x2A
#define ST7789_RASET 0x2B
#define ST7789_RAMWR 0x2C
#define ST7789_RAMRD 0x2E
int st7789_init();
void LcdWriteReg(uint8_t Data);
void LcdWriteData(uint8_t Data);
void LcdWriteDataMultiple(uint8_t * pData, int NumItems);
#endif /* __ST7789_H */

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NAME := developerkit
$(NAME)_TYPE := kernel
MODULE := 1062
HOST_ARCH := Cortex-M4
HOST_MCU_FAMILY := stm32l4xx_cube
SUPPORT_BINS := no
ENABLE_VFP := 1
HOST_MCU_NAME := STM32L496VGTx
$(NAME)_SOURCES += aos/board.c \
aos/board_cli.c \
aos/soc_init.c
$(NAME)_SOURCES += Src/stm32l4xx_hal_msp.c
ifeq ($(COMPILER), armcc)
$(NAME)_SOURCES += startup_stm32l496xx_keil.s
else ifeq ($(COMPILER), iar)
$(NAME)_SOURCES += startup_stm32l496xx_iar.s
else
$(NAME)_SOURCES += startup_stm32l496xx.s
endif
GLOBAL_INCLUDES += . \
hal/ \
aos/ \
Inc/
GLOBAL_CFLAGS += -DSTM32L496xx
GLOBAL_DEFINES += STDIO_UART=6
GLOBAL_DEFINES += CONFIG_AOS_CLI_BOARD
#$(NAME)_COMPONENTS += sensor
#GLOBAL_DEFINES += AOS_SENSOR_ACC_MIR3_DA217
#GLOBAL_DEFINES += AOS_SENSOR_ALS_LITEON_LTR553
#GLOBAL_DEFINES += AOS_SENSOR_PS_LITEON_LTR553
ifeq ($(COMPILER),armcc)
GLOBAL_LDFLAGS += -L --scatter=board/developerkit/STM32L496.sct
else ifeq ($(COMPILER),iar)
GLOBAL_LDFLAGS += --config STM32L496.icf
else
GLOBAL_LDFLAGS += -T board/developerkit/STM32L496VGTx_FLASH.ld
endif
sal ?= 1
ifeq (1,$(sal))
$(NAME)_COMPONENTS += sal
module ?= wifi.mk3060
else
GLOBAL_DEFINES += CONFIG_NO_TCPIP
endif
ifeq ($(COMPILER),armcc)
$(NAME)_LINK_FILES := startup_stm32l496xx_keil.o
$(NAME)_LINK_FILES += Src/stm32l4xx_hal_msp.o
endif
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_developerkit
CONFIG_SYSINFO_DEVICE_NAME := developerkit
GLOBAL_CFLAGS += -DSYSINFO_OS_VERSION=\"$(CONFIG_SYSINFO_OS_VERSION)\"
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_ADC_STM32L4_H
#define __HAL_ADC_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include "aos/kernel.h"
#define PORT_ADC1 1
#define PORT_ADC2 2
#define PORT_ADC3 3
#define PORT_ADC4 4
#define PORT_ADC5 5
#define PORT_ADC6 6
#define PORT_ADC7 7
#define PORT_ADC8 8
#ifdef __cplusplus
}
#endif
#endif /* __HAL_UART_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_GPIO_STM32L4_H
#define __HAL_GPIO_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include "aos/kernel.h"
#define PINS_IN_GROUP 16
#define GROUP_GPIOA 0
#define GROUP_GPIOB 1
#define GROUP_GPIOC 2
#define GROUP_GPIOD 3
#define GROUP_GPIOE 4
#define HAL_GPIO_0 ((uint8_t)0) /* represent GPIOA pin 0 */
#define HAL_GPIO_1 ((uint8_t)1) /* represent GPIOA pin 1 */
#define HAL_GPIO_2 ((uint8_t)2) /* represent GPIOA pin 2 */
#define HAL_GPIO_3 ((uint8_t)3) /* represent GPIOA pin 3 */
#define HAL_GPIO_4 ((uint8_t)4) /* represent GPIOA pin 4 */
#define HAL_GPIO_5 ((uint8_t)5) /* represent GPIOA pin 5 */
#define HAL_GPIO_6 ((uint8_t)6) /* represent GPIOA pin 6 */
#define HAL_GPIO_7 ((uint8_t)7) /* represent GPIOA pin 7 */
#define HAL_GPIO_8 ((uint8_t)8) /* represent GPIOA pin 8 */
#define HAL_GPIO_9 ((uint8_t)9) /* represent GPIOA pin 9 */
#define HAL_GPIO_10 ((uint8_t)10) /* represent GPIOA pin 10 */
#define HAL_GPIO_11 ((uint8_t)11) /* represent GPIOA pin 11 */
#define HAL_GPIO_12 ((uint8_t)12) /* represent GPIOA pin 12 */
#define HAL_GPIO_13 ((uint8_t)13) /* represent GPIOA pin 13 */
#define HAL_GPIO_14 ((uint8_t)14) /* represent GPIOA pin 14 */
#define HAL_GPIO_15 ((uint8_t)15) /* represent GPIOA pin 15 */
#define HAL_GPIO_16 ((uint8_t)16) /* represent GPIOB pin 0 */
#define HAL_GPIO_17 ((uint8_t)17) /* represent GPIOB pin 1 */
#define HAL_GPIO_18 ((uint8_t)18) /* represent GPIOB pin 2 */
#define HAL_GPIO_19 ((uint8_t)19) /* represent GPIOB pin 3 */
#define HAL_GPIO_20 ((uint8_t)20) /* represent GPIOB pin 4 */
#define HAL_GPIO_21 ((uint8_t)21) /* represent GPIOB pin 5 */
#define HAL_GPIO_22 ((uint8_t)22) /* represent GPIOB pin 6 */
#define HAL_GPIO_23 ((uint8_t)23) /* represent GPIOB pin 7 */
#define HAL_GPIO_24 ((uint8_t)24) /* represent GPIOB pin 8 */
#define HAL_GPIO_25 ((uint8_t)25) /* represent GPIOB pin 9 */
#define HAL_GPIO_26 ((uint8_t)26) /* represent GPIOB pin 10 */
#define HAL_GPIO_27 ((uint8_t)27) /* represent GPIOB pin 11 */
#define HAL_GPIO_28 ((uint8_t)28) /* represent GPIOB pin 12 */
#define HAL_GPIO_29 ((uint8_t)29) /* represent GPIOB pin 13 */
#define HAL_GPIO_30 ((uint8_t)30) /* represent GPIOB pin 14 */
#define HAL_GPIO_31 ((uint8_t)31) /* represent GPIOB pin 15 */
#define HAL_GPIO_32 ((uint8_t)32) /* represent GPIOC pin 0 */
#define HAL_GPIO_33 ((uint8_t)33) /* represent GPIOC pin 1 */
#define HAL_GPIO_34 ((uint8_t)34) /* represent GPIOC pin 2 */
#define HAL_GPIO_35 ((uint8_t)35) /* represent GPIOC pin 3 */
#define HAL_GPIO_36 ((uint8_t)36) /* represent GPIOC pin 4 */
#define HAL_GPIO_37 ((uint8_t)37) /* represent GPIOC pin 5 */
#define HAL_GPIO_38 ((uint8_t)38) /* represent GPIOC pin 6 */
#define HAL_GPIO_39 ((uint8_t)39) /* represent GPIOC pin 7 */
#define HAL_GPIO_40 ((uint8_t)40) /* represent GPIOC pin 8 */
#define HAL_GPIO_41 ((uint8_t)41) /* represent GPIOC pin 9 */
#define HAL_GPIO_42 ((uint8_t)42) /* represent GPIOC pin 10 */
#define HAL_GPIO_43 ((uint8_t)43) /* represent GPIOC pin 11 */
#define HAL_GPIO_44 ((uint8_t)44) /* represent GPIOC pin 12 */
#define HAL_GPIO_45 ((uint8_t)45) /* represent GPIOC pin 13 */
#define HAL_GPIO_46 ((uint8_t)46) /* represent GPIOC pin 14 */
#define HAL_GPIO_47 ((uint8_t)47) /* represent GPIOC pin 15 */
#define SW_FUNC_B HAL_GPIO_45
#define LCD_PWR HAL_GPIO_0
#define LCD_RST HAL_GPIO_1
#define LCD_NSS HAL_GPIO_4
#define LCD_SCK HAL_GPIO_5
#define LCD_TX HAL_GPIO_7
#define SW_WIFI HAL_GPIO_16
#define LCD_DCX HAL_GPIO_17
#define LED_GS HAL_GPIO_18
#define AUDIO_EN HAL_GPIO_8
#define SW_FUNC_A HAL_GPIO_11
#define LED_PS HAL_GPIO_12
#define LED_HTS HAL_GPIO_15
#define WIFI_RST HAL_GPIO_20
#define LED_ALS HAL_GPIO_21
#define WIFI_TX HAL_GPIO_22
#define WIFI_RX HAL_GPIO_23
#define ALS_INT HAL_GPIO_24
#define WIFI_WU HAL_GPIO_25
#define GPIOA_SPEED GPIO_SPEED_FREQ_VERY_HIGH
#ifdef __cplusplus
}
#endif
#endif /* __HAL_GPIO_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_I2C_STM32L4_H
#define __HAL_I2C_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
/******************************** I2C1 configure *****************************/
#define AOS_PORT_I2C1 1
#define I2C1_INSTANCE I2C1
#define I2C1_TIMING 0x40403E5D
#define I2C1_OWN_ADDRESS1 0x70
#define I2C1_ADDRESSING_MODE I2C_ADDRESSINGMODE_7BIT
#define I2C1_DUAL_ADDRESS_MODE I2C_DUALADDRESS_DISABLE
#define I2C1_OWNADDRESS2 0xFF
#define I2C1_OWN_ADDRESS2_MASK I2C_OA2_NOMASK
#define I2C1_GENERAL_CALL_MODE I2C_GENERALCALL_DISABLE
#define I2C1_NO_STRETCH_MODE I2C_NOSTRETCH_DISABLE
/* Definition for I2C1 clock resources */
#define I2C1_RCC_PERIPH_CLOCK_SELECTION RCC_PERIPHCLK_I2C1
#define I2C1_RCC_CLOCK_SELECTION RCC_I2C1CLKSOURCE_SYSCLK
#define I2C1_CLK_ENABLE() __HAL_RCC_I2C1_CLK_ENABLE()
#define I2C1_CLK_DISABLE() __HAL_RCC_I2C1_CLK_DISABLE()
#define I2C1_SDA_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
#define I2C1_SCL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
#define I2C1_SDA_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE()
#define I2C1_SCL_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE()
#define I2C1_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
#define I2C1_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
/* Definition for I2C1 Pins */
#define I2C1_GPIO_SCL_PIN GPIO_PIN_14
#define I2C1_GPIO_SDA_PIN GPIO_PIN_13
#define I2C1_GPIO_SCL_PORT GPIOG
#define I2C1_GPIO_SDA_PORT GPIOG
#define I2C1_GPIO_MODE GPIO_MODE_AF_OD
#define I2C1_GPIO_PULL GPIO_PULLUP
#define I2C1_GPIO_SPEED GPIO_SPEED_FREQ_VERY_HIGH
#define I2C1_GPIO_ALTERNATE GPIO_AF4_I2C1
/* Definition for I2C1's NVIC */
#define I2C1_EV_IRQn I2C1_EV_IRQn
#define I2C1_ER_IRQn I2C1_ER_IRQn
/******************************** I2C2 configure *****************************/
#define AOS_PORT_I2C2 2
#define I2C2_INSTANCE I2C2
#define I2C2_TIMING 0x40403E5D
#define I2C2_OWN_ADDRESS1 0x70
#define I2C2_ADDRESSING_MODE I2C_ADDRESSINGMODE_7BIT
#define I2C2_DUAL_ADDRESS_MODE I2C_DUALADDRESS_DISABLE
#define I2C2_OWNADDRESS2 0xFF
#define I2C2_OWN_ADDRESS2_MASK I2C_OA2_NOMASK
#define I2C2_GENERAL_CALL_MODE I2C_GENERALCALL_DISABLE
#define I2C2_NO_STRETCH_MODE I2C_NOSTRETCH_DISABLE
/* Definition for I2C2 clock resources */
#define I2C2_RCC_PERIPH_CLOCK_SELECTION RCC_PERIPHCLK_I2C2
#define I2C2_RCC_CLOCK_SELECTION RCC_I2C2CLKSOURCE_SYSCLK
#define I2C2_CLK_ENABLE() __HAL_RCC_I2C2_CLK_ENABLE()
#define I2C2_CLK_DISABLE() __HAL_RCC_I2C2_CLK_DISABLE()
#define I2C2_SDA_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define I2C2_SCL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()
#define I2C2_SDA_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define I2C2_SCL_GPIO_CLK_DISABLE() __HAL_RCC_GPIOH_CLK_DISABLE()
#define I2C2_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
#define I2C2_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
/* Definition for I2C2 Pins */
#define I2C2_GPIO_SCL_PIN GPIO_PIN_4
#define I2C2_GPIO_SDA_PIN GPIO_PIN_14
#define I2C2_GPIO_SCL_PORT GPIOH
#define I2C2_GPIO_SDA_PORT GPIOB
#define I2C2_GPIO_MODE GPIO_MODE_AF_OD
#define I2C2_GPIO_PULL GPIO_PULLUP
#define I2C2_GPIO_SPEED GPIO_SPEED_FREQ_VERY_HIGH
#define I2C2_GPIO_ALTERNATE GPIO_AF4_I2C2
/* Definition for I2C2's NVIC */
#define I2C2_EV_IRQn I2C2_EV_IRQn
#define I2C2_ER_IRQn I2C2_ER_IRQn
#ifdef __cplusplus
}
#endif
#endif /* __HAL_I2C_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_NAND_STM32L4_H
#define __HAL_NAND_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include "hal/soc/soc.h"
#if defined(STM32L496xx)
#include "stm32l496xx.h"
#endif
#define NAND_HANDLE_INSTANCE FMC_NAND_DEVICE
#define NAND_INIT_NAND_BANK FMC_NAND_BANK3
#define NAND_INIT_WAIT_FEATURE FMC_NAND_WAIT_FEATURE_ENABLE
#define NAND_INIT_MEMORY_DATA_WIDTH FMC_NAND_MEM_BUS_WIDTH_8
#define NAND_INIT_ECC_COMPUTATION FMC_NAND_ECC_ENABLE
#define NAND_INIT_ECC_PAGE_SIZE FMC_NAND_ECC_PAGE_SIZE_512BYTE
#define NAND_INIT_TCLR_SETUP_TIME 0
#define NAND_INIT_TAR_SETUP_TIME 0
#define NAND_INFO_PAGE_SIZE 0x800
#define NAND_INFO_SPARE_AREA_SIZE 0x40
#define NAND_INFO_BLOCK_SIZE 0x40
#define NAND_INFO_BLOCK_NBR 0x400
#define NAND_INFO_ZONE_SIZE 0x400
#define COM_SPACE_SETUP_TIME 0x5
#define COM_SPACE_WAIT_TIME 0x4
#define COM_SPACE_HOLD_TIME 0x2
#define COM_SPACE_HIZ_TIME 0x5
#define ATT_SPACE_SETUP_TIME 0x5
#define ATT_SPACE_WAIT_TIME 0x4
#define ATT_SPACE_HOLD_TIME 0x2
#define ATT_SPACE_HIZ_TIME 0x5
#ifdef __cplusplus
}
#endif
#endif /* __HAL_NAND_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_NOR_STM32L4_H
#define __HAL_NOR_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include "hal/soc/soc.h"
#if defined(STM32L496xx)
#include "stm32l496xx.h"
#endif
#define NOR_DEVICE_ADDR ((uint32_t)0x64000000)
/* NOR size configuration */
#define NOR_BLOCK_SIZE 0x1000
#define NOR_CHIP_SIZE
/* NOR operations Timeout definitions */
#define BLOCKERASE_TIMEOUT 2000U /* NOR block erase timeout : 2 s */
#define CHIPERASE_TIMEOUT 400000U /* NOR chip erase timeout : 400 s */
#define PROGRAM_TIMEOUT 13U /* NOR program timeout : 64 bytes * 200 us = 12.8 ms */
#define NOR_HANDLE_INSTANCE FMC_NORSRAM_DEVICE
#define NOR_HANDLE_EXTENDED FMC_NORSRAM_EXTENDED_DEVICE
#define NOR_ADDR_SETUP_TIME 0x1
#define NOR_ADDR_HOLD_TIME 0x1
#define NOR_DATA_SETUP_TIME 0x6
#define NOR_BUS_TURN_DURATION 0x0
#define NOR_CLK_DIVISION 0x2
#define NOR_DATA_LATENCY 0x2
#define NOR_ACCESS_MODE FMC_ACCESS_MODE_B
#define NOR_INIT_NSBANK FMC_NORSRAM_BANK2
#define NOR_INIT_DATA_ADDR_MUX FMC_DATA_ADDRESS_MUX_DISABLE
#define NOR_INIT_MEMORY_TYPE FMC_MEMORY_TYPE_NOR
#define NOR_INIT_MEM_DATA_WIDTH FMC_NORSRAM_MEM_BUS_WIDTH_16
#define NOR_INIT_BURST_ACCESS_MODE FMC_BURST_ACCESS_MODE_DISABLE
#define NOR_INIT_WAIT_SIGNAL_PRI FMC_WAIT_SIGNAL_POLARITY_LOW
#define NOR_INIT_WAIT_SIGNAL_ACT FMC_WAIT_TIMING_BEFORE_WS
#define NOR_INIT_WRITE_OPERATION FMC_WRITE_OPERATION_ENABLE
#define NOR_INIT_WAIT_SIGNAL FMC_WAIT_SIGNAL_DISABLE
#define NOR_INIT_EXTENDED_MODE FMC_EXTENDED_MODE_DISABLE
#define NOR_INIT_ASYNC_WAIT FMC_ASYNCHRONOUS_WAIT_DISABLE
#define NOR_INIT_WRITE_BURST FMC_WRITE_BURST_DISABLE
#define NOR_INIT_CONTINUOUS_CLK FMC_CONTINUOUS_CLOCK_SYNC_ONLY
#define NOR_INIT_PAGE_SIZE FMC_PAGE_SIZE_NONE
#ifdef __cplusplus
}
#endif
#endif /* __HAL_NOR_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_QSPI_STM32L4_H
#define __HAL_QSPI_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include "aos/kernel.h"
/* qspi port defines */
#define PORT_QSPI1 1
#define PORT_QSPI2 2
#define PORT_QSPI3 3
#define PORT_QSPI4 4
/* cmd defines in function hal_qspi_command */
#define CMD_QUAD_PAGE_PROG 1
/* cmd defines in function hal_qspi_autoPolling */
#define AP_GET_MEM_STATUS 1
#define AP_GET_WRITE_ENABLE_STATUS 2
#ifdef __cplusplus
}
#endif
#endif /* __HAL_QSPI_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_ADC_STM32L4_H
#define __HAL_ADC_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include "aos/kernel.h"
#define RTC_ASYNCH_PREDIV 0x7F
#define RTC_SYNCH_PREDIV 0xF9
#define RTC_INIT_HOUR_FORMAT RTC_HOURFORMAT_24
#define RTC_INIT_ASYNC_PREDIV RTC_ASYNCH_PREDIV
#define RTC_INIT_SYNC_PREDIV RTC_SYNCH_PREDIV
#define RTC_INIT_OUTPUT RTC_OUTPUT_DISABLE
#define RTC_INIT_OUTPUT_PRI RTC_OUTPUT_POLARITY_HIGH
#define RTC_INIT_OUTPUT_TYPE RTC_OUTPUT_TYPE_OPENDRAIN
#ifdef __cplusplus
}
#endif
#endif /* __HAL_UART_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_SD_STM32L4_H
#define __HAL_SD_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include "hal/soc/soc.h"
#if defined(STM32L496xx)
#include "stm32l496xx.h"
#endif
#define SD_INSTANCE SDMMC1
#define SD_INIT_CLK_EDGE SDMMC_CLOCK_EDGE_RISING
#define SD_INIT_CLK_BYPASS SDMMC_CLOCK_BYPASS_DISABLE
#define SD_INIT_CLK_POWER_SAVE SDMMC_CLOCK_POWER_SAVE_DISABLE
#define SD_INIT_BUS_WIDE SDMMC_BUS_WIDE_1B
#define SD_INIT_HW_FLOW_CTRL SDMMC_HARDWARE_FLOW_CONTROL_ENABLE
#define SD_INIT_CLK_DIVISION SDMMC_TRANSFER_CLK_DIV
#ifdef __cplusplus
}
#endif
#endif /* __HAL_SD_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_SPI_STM32L4_H
#define __HAL_SPI_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include "aos/kernel.h"
#define PORT_SPI1 1
#define PORT_SPI2 2
#define PORT_SPI3 3
#define PORT_SPI4 4
#ifdef __cplusplus
}
#endif
#endif /* __HAL_SPI_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_TIMER_STM32L4_H
#define __HAL_TIMER_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l4xx_hal.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include "aos/kernel.h"
#define PORT_TIMER1 1
#define PORT_TIMER2 2
#define PORT_TIMER3 3
#define PORT_TIMER4 4
#ifdef __cplusplus
}
#endif
#endif /* __HAL_TIMER_STM32L4_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef __HAL_UART_STM32L4_H
#define __HAL_UART_STM32L4_H
#ifdef __cplusplus
extern "C" {
#endif
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include "aos/kernel.h"
#include "hal/hal.h"
/***************************** usart1 configure *******************************/
#define UART1 USART1
#define UART1_BANDRATE 115200
#define UART1_WORD_LENGTH UART_WORDLENGTH_8B
#define UART1_STOP_BITS UART_STOPBITS_1
#define UART1_PARITY UART_PARITY_NONE
#define UART1_MODE UART_MODE_TX_RX
#define UART1_HW_FLOW_CTL UART_HWCONTROL_NONE
#define UART1_OVER_SAMPLING UART_OVERSAMPLING_16
#define UART1_ONE_BIT_SAMPLING UART_ONE_BIT_SAMPLE_DISABLE
#define UART1_ADV_FEATURE_INIT UART_ADVFEATURE_NO_INIT
#define UART1_IRQn USART1_IRQn
#define UART1_CLK_ENABLE()
#define UART1_CLK_DISABLE()
#define UART1_TX_GPIO_CLK_ENABLE()
#define UART1_TX_GPIO_CLK_DISABLE()
#define UART1_RX_GPIO_CLK_ENABLE()
#define UART1_RX_GPIO_CLK_DISABLE()
/***************************** usart2 configure *******************************/
#define UART2 USART2
#define UART2_BANDRATE 115200
#define UART2_WORD_LENGTH UART_WORDLENGTH_8B
#define UART2_STOP_BITS UART_STOPBITS_1
#define UART2_PARITY UART_PARITY_NONE
#define UART2_MODE UART_MODE_TX_RX
#define UART2_HW_FLOW_CTL UART_HWCONTROL_NONE
#define UART2_OVER_SAMPLING UART_OVERSAMPLING_16
#define UART2_ONE_BIT_SAMPLING UART_ONE_BIT_SAMPLE_DISABLE
#define UART2_ADV_FEATURE_INIT UART_ADVFEATURE_NO_INIT
#define UART2_IRQn USART2_IRQn
#define UART2_CLK_ENABLE()
#define UART2_CLK_DISABLE()
#define UART2_TX_GPIO_CLK_ENABLE()
#define UART2_TX_GPIO_CLK_DISABLE()
#define UART2_RX_GPIO_CLK_ENABLE()
#define UART2_RX_GPIO_CLK_DISABLE()
/***************************** usart3 configure *******************************/
#define UART3 USART3
#define UART3_BANDRATE 115200
#define UART3_WORD_LENGTH UART_WORDLENGTH_8B
#define UART3_STOP_BITS UART_STOPBITS_1
#define UART3_PARITY UART_PARITY_NONE
#define UART3_MODE UART_MODE_TX_RX
#define UART3_HW_FLOW_CTL UART_HWCONTROL_NONE
#define UART3_OVER_SAMPLING UART_OVERSAMPLING_16
#define UART3_ONE_BIT_SAMPLING UART_ONE_BIT_SAMPLE_DISABLE
#define UART3_ADV_FEATURE_INIT UART_ADVFEATURE_NO_INIT
#define UART3_IRQn USART3_IRQn
#define UART3_CLK_ENABLE()
#define UART3_CLK_DISABLE()
#define UART3_TX_GPIO_CLK_ENABLE()
#define UART3_TX_GPIO_CLK_DISABLE()
#define UART3_RX_GPIO_CLK_ENABLE()
#define UART3_RX_GPIO_CLK_DISABLE()
/***************************** uart4 configure *******************************/
//#define UART4 UART4
#define UART4_BANDRATE 115200
#define UART4_WORD_LENGTH UART_WORDLENGTH_8B
#define UART4_STOP_BITS UART_STOPBITS_1
#define UART4_PARITY UART_PARITY_NONE
#define UART4_MODE UART_MODE_TX_RX
#define UART4_HW_FLOW_CTL UART_HWCONTROL_NONE
#define UART4_OVER_SAMPLING UART_OVERSAMPLING_16
#define UART4_ONE_BIT_SAMPLING UART_ONE_BIT_SAMPLE_DISABLE
#define UART4_ADV_FEATURE_INIT UART_ADVFEATURE_NO_INIT
#define UART4_IRQn UART4_IRQn
#define UART4_CLK_ENABLE()
#define UART4_CLK_DISABLE()
#define UART4_TX_GPIO_CLK_ENABLE()
#define UART4_TX_GPIO_CLK_DISABLE()
#define UART4_RX_GPIO_CLK_ENABLE()
#define UART4_RX_GPIO_CLK_DISABLE()
/***************************** uart5 configure *******************************/
//#define UART5 UART5
#define UART5_BANDRATE 115200
#define UART5_WORD_LENGTH UART_WORDLENGTH_8B
#define UART5_STOP_BITS UART_STOPBITS_1
#define UART5_PARITY UART_PARITY_NONE
#define UART5_MODE UART_MODE_TX_RX
#define UART5_HW_FLOW_CTL UART_HWCONTROL_NONE
#define UART5_OVER_SAMPLING UART_OVERSAMPLING_16
#define UART5_ONE_BIT_SAMPLING UART_ONE_BIT_SAMPLE_DISABLE
#define UART5_ADV_FEATURE_INIT UART_ADVFEATURE_NO_INIT
#define UART5_IRQn UART5_IRQn
#define UART5_CLK_ENABLE()
#define UART5_CLK_DISABLE()
#define UART5_TX_GPIO_CLK_ENABLE()
#define UART5_TX_GPIO_CLK_DISABLE()
#define UART5_RX_GPIO_CLK_ENABLE()
#define UART5_RX_GPIO_CLK_DISABLE()
/***************************** lpuart1 configure *******************************/
#define UART6 LPUART1
#define UART6_BANDRATE 115200
#define UART6_WORD_LENGTH UART_WORDLENGTH_8B
#define UART6_STOP_BITS UART_STOPBITS_1
#define UART6_PARITY UART_PARITY_NONE
#define UART6_MODE UART_MODE_TX_RX
#define UART6_HW_FLOW_CTL UART_HWCONTROL_NONE
#define UART6_OVER_SAMPLING UART_OVERSAMPLING_16
#define UART6_ONE_BIT_SAMPLING UART_ONE_BIT_SAMPLE_DISABLE
#define UART6_ADV_FEATURE_INIT UART_ADVFEATURE_NO_INIT
#define UART6_IRQn LPUART1_IRQn
#define UART6_CLK_ENABLE()
#define UART6_CLK_DISABLE()
#define UART6_TX_GPIO_CLK_ENABLE()
#define UART6_TX_GPIO_CLK_DISABLE()
#define UART6_RX_GPIO_CLK_ENABLE()
#define UART6_RX_GPIO_CLK_DISABLE()
#define MAX_BUF_UART_BYTES 1024
#ifdef __cplusplus
}
#endif
#endif /* __HAL_UART_STM32L4_H */

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/**
******************************************************************************
* @file startup_stm32l496xx.s
* @author MCD Application Team
* @brief STM32L496xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word TAMP_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word DFSDM1_FLT3_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word SDMMC1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word DFSDM1_FLT0_IRQHandler
.word DFSDM1_FLT1_IRQHandler
.word DFSDM1_FLT2_IRQHandler
.word COMP_IRQHandler
.word LPTIM1_IRQHandler
.word LPTIM2_IRQHandler
.word OTG_FS_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word LPUART1_IRQHandler
.word QUADSPI_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word SAI1_IRQHandler
.word SAI2_IRQHandler
.word SWPMI1_IRQHandler
.word TSC_IRQHandler
.word LCD_IRQHandler
.word 0
.word RNG_IRQHandler
.word FPU_IRQHandler
.word CRS_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word DCMI_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word DMA2D_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TSC_IRQHandler
.thumb_set TSC_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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;********************** COPYRIGHT(c) 2017 STMicroelectronics ******************
;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team
;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DCMI_IRQHandler ; DCMI global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
DFSDM1_FLT3_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
COMP_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
OTG_FS_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
LPUART1_IRQHandler
QUADSPI_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SAI1_IRQHandler
SAI2_IRQHandler
SWPMI1_IRQHandler
TSC_IRQHandler
LCD_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
CRS_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
DCMI_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

24
Living_SDK/board/eml3047/board.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include "hal/soc/soc.h"
#include <aos/kernel.h>
#include <aos/aos.h>
/* Logic partition on flash devices */
hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX] =
{
[HAL_PARTITION_PARAMETER_2] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "PARAMETER2",
.partition_start_addr = 0x8015000,
.partition_length = 0x2000, // 8k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
};
void board_init(void)
{
}

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Living_SDK/board/eml3047/board.h Normal file
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#define HARDWARE_REVISION "V1.0"
#define MODEL "EML3047"
#ifdef BOOTLOADER
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#else
#define STDIO_UART 0
#define STDIO_UART_BUADRATE 115200
#endif

69
Living_SDK/board/eml3047/eml3047.mk Normal file
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NAME := board_eml3047
JTAG := jlink_swd
$(NAME)_TYPE := kernel
MODULE := 1062
HOST_ARCH := Cortex-M0
HOST_MCU_FAMILY := stm32l0xx.stm32l071kb
SUPPORT_BINS := no
$(NAME)_SOURCES := board.c \
src/debug.c \
src/hw_gpio.c \
src/hw_spi.c \
src/hw_rtc.c \
src/eml3047_hw.c \
src/eml3047_it.c \
src/vcom.c \
src/lorawan_port.c \
../../device/lora/eml3047_lrwan/eml3047.c \
- ../../device/lora/sx1276/sx1276.c
#$(NAME)_COMPONENTS += modules.fs.kv
linkwan ?= 0
ifeq ($(linkwan), 0)
$(NAME)_SOURCES += src/lora.c
endif
#$(NAME)_LINK_FILES := src/eml3047_it.o
GLOBAL_INCLUDES += . \
inc \
../../platform/mcu/stm32l0xx/Drivers/STM32L0xx_HAL_Driver/Inc \
../../platform/mcu/stm32l0xx/Drivers/STM32L0xx_HAL_Driver/Inc/Legacy \
../../platform/mcu/stm32l0xx/Drivers/CMSIS/Device/ST/STM32L0xx/Include \
../../platform/mcu/stm32l0xx/Drivers/CMSIS/Include
GLOBAL_DEFINES += \
USE_HAL_DRIVER \
STM32L071xx
GLOBAL_INCLUDES += ../../device/lora/eml3047_lrwan \
../../device/lora/sx1276 \
GLOBAL_DEFINES += STDIO_UART=0 CONFIG_NO_TCPIP
GLOBAL_DEFINES += RHINO_CONFIG_TICK_TASK=0 RHINO_CONFIG_WORKQUEUE=0
GLOBAL_DEFINES += USE_FULL_LL_DRIVER USE_B_EML3047
CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_EML3047
CONFIG_SYSINFO_DEVICE_NAME := EML3047
GLOBAL_CFLAGS += -DSYSINFO_OS_VERSION=\"$(CONFIG_SYSINFO_OS_VERSION)\"
GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\"
GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\"
GLOBAL_LDFLAGS += -L $(SOURCE_ROOT)/board/eml3047
# Global defines
# HSE_VALUE = STM32 crystal frequency = 26MHz (needed to make UART work correctly)
GLOBAL_DEFINES += $$(if $$(NO_CRLF_STDIO_REPLACEMENT),,CRLF_STDIO_REPLACEMENT)
GLOBAL_CFLAGS += -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft
WIFI_FIRMWARE_SECTOR_START := 2 #0x2000
FILESYSTEM_IMAGE_SECTOR_START := 256 #0x100000
# Extra build target in mico_standard_targets.mk, include bootloader, and copy output file to eclipse debug file (copy_output_for_eclipse)
EXTRA_TARGET_MAKEFILES += $(MAKEFILES_PATH)/aos_standard_targets.mk
#EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/gen_crc_bin.mk

158
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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2015 Semtech
Description: End device comissioning parameters
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file comissioning.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief End device comissioning parameters
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __LORA_COMISSIONING_H__
#define __LORA_COMISSIONING_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* When set to 1 the application uses the Over-the-Air activation procedure
* When set to 0 the application uses the Personalization activation procedure
*/
#define OVER_THE_AIR_ACTIVATION 1
/**
* Indicates if the end-device is to be connected to a private or public network
*/
#define LORAWAN_PUBLIC_NETWORK true
/**
* When set to 1 DevEui is LORAWAN_DEVICE_EUI
* When set to 0 DevEui is automatically generated by calling
* BoardGetUniqueId function
*/
#define STATIC_DEVICE_EUI 0
/**
* Mote device IEEE EUI (big endian)
*
* \remark see STATIC_DEVICE_EUI comments
*/
#define LORAWAN_DEVICE_EUI { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }
/**
* Application IEEE EUI (big endian)
*/
#define LORAWAN_APPLICATION_EUI { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }
/**
* AES encryption/decryption cipher application key
*/
#define LORAWAN_APPLICATION_KEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
/**
* Current network ID
*/
#define LORAWAN_NETWORK_ID ( uint32_t )0
/**
* When set to 1 DevAdd is LORAWAN_DEVICE_ADDRESS
* When set to 0 DevAdd is automatically generated using
* a pseudo random generator seeded with a value derived from
* BoardUniqueId value
*/
#define STATIC_DEVICE_ADDRESS 0
/**
* Device address on the network (big endian)
*
* \remark see STATIC_DEVICE_ADDRESS comments
*/
#define LORAWAN_DEVICE_ADDRESS ( uint32_t )0x0100000a
/**
* AES encryption/decryption cipher network session key
*/
#define LORAWAN_NWKSKEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
/**
* AES encryption/decryption cipher application session key
*/
#define LORAWAN_APPSKEY { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }
/**
* Multicast address
*/
#define LORAWAN_MULTICAST_ADDRESS 0x06344bf2
/**
* AES encryption/decryption cipher network session key for multicast
*/
#define LORAWAN_MULTICAST_NWKSKEY { 0x65, 0xe4, 0x48, 0x3d, 0xe3, 0xa9, 0xce, 0xb1, 0x50, 0xd8, 0x86, 0xf3, 0x61, 0x46, 0x02, 0xb5 }
/**
* AES encryption/decryption cipher application session key for multicast
*/
#define LORAWAN_MULTICAST_APPSKEY { 0xc2, 0x65, 0x67, 0xa3, 0xec, 0xd3, 0x96, 0x67, 0xd6, 0x23, 0xf8, 0x7a, 0xe1, 0x6c, 0x12, 0x23 }
#ifdef __cplusplus
}
#endif
#endif /* __LORA_COMISSIONING_H__ */

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/******************************************************************************
* @file debug.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief Header for driver debug.c module
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DEBUG_H__
#define __DEBUG_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <string.h>
#include <stdio.h>
#include "hw_conf.h"
#include "vcom.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
#ifdef LORA_DEBUG
#define DBG_GPIO_WRITE(gpio, n, x) HW_GPIO_Write(gpio, n, (GPIO_PinState)(x))
#define DBG_GPIO_SET(gpio, n) gpio->BSRR = n
#define DBG_GPIO_RST(gpio, n) gpio->BRR = n
#define DBG_RTC_OUTPUT LL_RTC_ALARMOUT_DISABLE /* LL_RTC_ALARMOUT_ALMA on PC13 */
#define DBG(x) do { x } while (0)
#ifdef LORA_TRACE
#include "hw_rtc.h"
#define DBG_PRINTF(format, ...) do {DBG_Send("[%d][%s:%4d] " format "", HW_RTC_GetTimerValue(), __FILE__, __LINE__, ##__VA_ARGS__);}while(0==1)//DBG_Send(__VA_ARGS__)//vcom_Send(__VA_ARGS__)
#define LOG_PRINTF(format, ...) do {DBG_Send(format, HW_RTC_GetTimerValue(), ##__VA_ARGS__);}while(0==1)
#define DBG_PRINTF_CRITICAL(...)
#else /*TRACE*/
#define DBG_PRINTF(...)
#define DBG_PRINTF_CRITICAL(...)
#endif /*TRACE*/
#else /* DEBUG */
#define DBG_GPIO_WRITE(gpio, n, x)
#define DBG_GPIO_SET(gpio, n)
#define DBG_GPIO_RST(gpio, n)
#define DBG(x) do { } while (0)
#define DBG_PRINTF(...)
#define DBG_PRINTF_CRITICAL(...)
#define DBG_RTC_OUTPUT LL_RTC_ALARMOUT_DISABLE
#endif /* DEBUG */
/* Exported functions ------------------------------------------------------- */
/**
* @brief Initializes the debug
* @param None
* @retval None
*/
void DBG_Init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DEBUG_H__*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: contains hardaware configuration Macros and Constants
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file eml3047_hw_conf.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief contains hardaware configuration Macros and Constants
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __EML3047_HW_CONF_H__
#define __EML3047_HW_CONF_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* LORA I/O definition */
#define RADIO_RESET_PORT GPIOB
#define RADIO_RESET_PIN GPIO_PIN_0
#define RADIO_MOSI_PORT GPIOB
#define RADIO_MOSI_PIN GPIO_PIN_5
#define RADIO_MISO_PORT GPIOB
#define RADIO_MISO_PIN GPIO_PIN_4
#define RADIO_SCLK_PORT GPIOA
#define RADIO_SCLK_PIN GPIO_PIN_5
#define RADIO_NSS_PORT GPIOA
#define RADIO_NSS_PIN GPIO_PIN_4
#define RADIO_DIO_0_PORT GPIOB
#define RADIO_DIO_0_PIN GPIO_PIN_6
#define RADIO_DIO_1_PORT GPIOA
#define RADIO_DIO_1_PIN GPIO_PIN_12
#define RADIO_DIO_2_PORT GPIOA
#define RADIO_DIO_2_PIN GPIO_PIN_11
#define RADIO_DIO_3_PORT GPIOA
#define RADIO_DIO_3_PIN GPIO_PIN_8
#ifdef RADIO_DIO_4
#define RADIO_DIO_4_PORT GPIOA
#define RADIO_DIO_4_PIN GPIO_PIN_9
#endif
#ifdef RADIO_DIO_5
#define RADIO_DIO_5_PORT GPIOC
#define RADIO_DIO_5_PIN GPIO_PIN_7
#endif
//#define RADIO_TCXO_VCC_PORT GPIOA
//#define RADIO_TCXO_VCC_PIN GPIO_PIN_12
#define RADIO_ANT_SWITCH_PORT GPIOA
#define RADIO_ANT_SWITCH_PIN GPIO_PIN_7
#define BAT_LEVEL_PORT GPIOA
#define BAT_LEVEL_PIN GPIO_PIN_4
/* SPI MACRO redefinition */
#define SPI_CLK_ENABLE() __HAL_RCC_SPI1_CLK_ENABLE()
#define SPI1_AF GPIO_AF0_SPI1
/* ADC MACRO redefinition */
#define BAT_LEVEL_PORT GPIOA //CRF2
#define BAT_LEVEL_PIN GPIO_PIN_4
#define ADC_READ_CHANNEL ADC_CHANNEL_4
#define ADCCLK_ENABLE() __HAL_RCC_ADC1_CLK_ENABLE();
#define ADCCLK_DISABLE() __HAL_RCC_ADC1_CLK_DISABLE();
/* --------------------------- RTC HW definition -------------------------------- */
#define RTC_OUTPUT DBG_RTC_OUTPUT
#define RTC_Alarm_IRQn RTC_IRQn
/* --------------------------- UART HW definition -------------------------------*/
/* Definition for UARTx clock resources */
#define UARTX LPUART1
#define UARTX_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPUART1)
#define UARTX_RX_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(RCC_IOPENR_GPIOBEN)
#define UARTX_TX_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(RCC_IOPENR_GPIOBEN)
#define UARTX_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1)
#define UARTX_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1)
#define UARTX_TX_PIN GPIO_PIN_2
#define UARTX_TX_GPIO_PORT GPIOA
#define UARTX_TX_AF GPIO_AF6_LPUART1
#define UARTX_RX_PIN GPIO_PIN_3
#define UARTX_RX_GPIO_PORT GPIOA
#define UARTX_RX_AF GPIO_AF6_LPUART1
/* Definition for USARTx's NVIC */
#define UARTX_IRQn LPUART1_IRQn
#define UARTX_IRQHandler LPUART1_IRQHandler
#ifdef __cplusplus
}
#endif
#endif /* __32L082MLM_HW_CONF_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: Bleeper board GPIO driver implementation
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file mlm32l0xx_it.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief manages interupt
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __32L082MLM_IT_H__
#define __32L082MLM_IT_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @brief RTC IRQ Handler on the RTC Alarm
* @param None
* @retval None
*/
void RTC_IRQHandler(void);
/**
* @brief Handles External lines 0 to 1 interrupt request.
* @param None
* @retval None
*/
void EXTI0_1_IRQHandler(void);
/**
* @brief Handles External lines 2 to 3 interrupt request.
* @param None
* @retval None
*/
void EXTI2_3_IRQHandler(void);
/**
* @brief Handles External lines 4 to 15 interrupt request.
* @param None
* @retval None
*/
void EXTI4_15_IRQHandler(void);
/**
* @brief vcom IRQ Handler
* @param None
* @retval None
*/
void UARTX_IRQHandler(void);
#ifdef __cplusplus
}
#endif
#endif /* __32L082MLM_IT_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: contains all hardware driver
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file hw.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief contains all hardware driver
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HW_H__
#define __HW_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <math.h>
#include <stdbool.h>
#include <stdint.h>
#include "hw_conf.h"
#include "hw_gpio.h"
#include "hw_spi.h"
#include "hw_rtc.h"
#include "hw_msp.h"
#include "debug.h"
#include "vcom.h"
typedef enum
{
HW_UNLOCKED = 0x00U,
HW_LOCKED = 0x01U
} HW_LockTypeDef;
#define HW_LOCK(__HANDLE__) \
do { \
if ((__HANDLE__)->Lock == HW_LOCKED) \
{ \
return; \
} \
else \
{ \
(__HANDLE__)->Lock = HW_LOCKED; \
} \
} while (0)
#define HW_UNLOCK(__HANDLE__) \
do { \
(__HANDLE__)->Lock = HW_UNLOCKED; \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* __HW_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: contains hardaware configuration Macros and Constants
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file hw_conf.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief contains hardware configuration Macros and Constants
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HW_CONF_H__
#define __HW_CONF_H__
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(USE_FULL_LL_DRIVER)
#error USE_FULL_LL_DRIVER must be defined
#endif
#if !defined(USE_B_EML3047)
#error Only USE_32L082MLM_DISCO is supported
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_ll_adc.h"
#include "stm32l0xx_ll_bus.h"
#include "stm32l0xx_ll_cortex.h"
#include "stm32l0xx_ll_exti.h"
#include "stm32l0xx_ll_gpio.h"
#include "stm32l0xx_ll_pwr.h"
#include "stm32l0xx_ll_rcc.h"
#include "stm32l0xx_ll_rtc.h"
#include "stm32l0xx_ll_spi.h"
#include "stm32l0xx_ll_system.h"
#include "stm32l0xx_ll_lpuart.h"
#include "stm32l0xx_ll_usart.h"
#include "eml3047_hw_conf.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/* --------Preprocessor compile swicth------------ */
/* debug swicthes in debug.h */
#ifdef CONFIG_LINKWAN_AT
#define LORA_DEBUG
#define LORA_TRACE
#endif
/* uncomment below line to never enter lowpower modes in main.c*/
/* #define LOW_POWER_DISABLE */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* __HW_CONF_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: Bleeper board GPIO driver implementation
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file hw_gpio.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief Header for driver hw_rtc.c module
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_ll_gpio.h"
/*
* Force the include of HAL GPIO in order to benefit from enum and structure
* definition which are used in LoRa modules
* Note that the code size is slighty increased by about 40 bytes on classA application because
* "Pin" of structure "GPIO_InitTypeDef" is not used in our HW_GPIO_xxx() implementation
*/
#include "stm32l0xx_hal_gpio.h"
#include "stm32l0xx_hal_gpio_ex.h"
/* Exported types ------------------------------------------------------------*/
typedef void ( GpioIrqHandler )(void);
/* Exported constants --------------------------------------------------------*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @brief Initializes the given GPIO object
*
* @param GPIOx: where x can be (A..E and H)
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* All port bits are not necessarily available on all GPIOs.
* @param [IN] initStruct GPIO_InitTypeDef intit structure
* @retval None
*/
void HW_GPIO_Init(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_InitTypeDef *initStruct);
/**
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices.
* Note that GPIOE is not available on all devices.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* All port bits are not necessarily available on all GPIOs.
* @retval None
* @note this is an implementation of HAL_GPIO_DeInit() using LL
*/
void HW_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin: Specifies the pins connected to the EXTI line.
* @retval None
* @note this is an implementation of HAL_GPIO_EXTI_IRQHandler() using LL
*/
void HW_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
/**
* @brief Records the interrupt handler for the GPIO object
*
* @param GPIOx: where x can be (A..E and H)
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* All port bits are not necessarily available on all GPIOs.
* @param [IN] prio NVIC priority (0 is highest)
* @param [IN] irqHandler points to the function to execute
* @retval None
*/
void HW_GPIO_SetIrq(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t prio, GpioIrqHandler *irqHandler);
/**
* @brief Execute the interrupt from the object
*
* @param GPIOx: where x can be (A..E and H)
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* All port bits are not necessarily available on all GPIOs.
* @retval None
*/
void HW_GPIO_IrqHandler(uint16_t GPIO_Pin);
/**
* @brief Writes the given value to the GPIO output
*
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* All port bits are not necessarily available on all GPIOs.
* @param [IN] value New GPIO output value
* @retval None
*/
__STATIC_INLINE void HW_GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t value)
{
/*
* Function HAL_GPIO_WritePin is inlined using LL Driver. It saves code size
* as the value to set is known at compile time most of the time
*/
if (value != RESET)
{
LL_GPIO_SetOutputPin(GPIOx, GPIO_Pin);
}
else
{
LL_GPIO_ResetOutputPin(GPIOx, GPIO_Pin);
}
}
/**
* @brief Reads the current GPIO input value
*
* @param GPIOx: where x can be (A..E and H)
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* All port bits are not necessarily available on all GPIOs.
* @retval value Current GPIO input value
*/
uint32_t HW_GPIO_Read(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
/**
* @brief Toggles the specified GPIO pins.
* @param GPIOx: Where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
* Note that GPIOE is not available on all devices.
* All port bits are not necessarily available on all GPIOs.
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
__STATIC_INLINE void HW_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
LL_GPIO_TogglePin(GPIOx, PinMask);
}
#ifdef __cplusplus
}
#endif
#endif /* __HW_GPIO_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: Header for driver hw msp module
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file hw_msp.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief Header for driver hw msp module
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HW_MSP_H__
#define __HW_MSP_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "hw_conf.h"
/* Exported types ------------------------------------------------------------*/
typedef enum
{
e_LOW_POWER_RTC = (1 << 0),
e_LOW_POWER_GPS = (1 << 1),
e_LOW_POWER_UART = (1 << 2), /* can be used to forbid stop mode in case of uart Xfer*/
} e_LOW_POWER_State_Id_t;
/* Exported constants --------------------------------------------------------*/
#define VDDA_VREFINT_CAL ((uint32_t) 3000)
#define BAT_CR2032 ((uint32_t) 3000)
#define VDD_BAT BAT_CR2032
#define VDD_MIN 1800
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/**
* @brief GPIOs Macro
*/
#define RCC_GPIO_CLK_ENABLE(__GPIO_PORT__) \
do { \
switch (__GPIO_PORT__) \
{ \
case GPIOA_BASE: LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); break; \
case GPIOB_BASE: LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); break; \
case GPIOC_BASE: LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOC); break; \
case GPIOD_BASE: LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOD); break; \
case GPIOH_BASE: default: LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOH); \
} \
} while (0)
#define RCC_GPIO_CLK_DISABLE(__GPIO_PORT__) \
do { \
switch (__GPIO_PORT__) \
{ \
case GPIOA_BASE: LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOA); break; \
case GPIOB_BASE: LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOB); break; \
case GPIOC_BASE: LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOC); break; \
case GPIOD_BASE: LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOD); break; \
case GPIOH_BASE: default: LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOH); \
} \
} while (0)
/* Exported functions ------------------------------------------------------- */
/**
* @brief This function return the battery level
* @param None
* @retval The battery level 0 (very low) to 254 (fully charged)
*/
uint8_t HW_GetBatteryLevel(void);
/**
* @brief Initializes the boards peripherals.
* @param None
* @retval None
*/
void HW_Init(void);
/**
* @brief De-initializes the target board peripherals to decrease power consumption.
* @param None
* @retval None
*/
void HW_DeInit(void);
/**
* @brief This function return a random seed
* @note Based on the device unique ID
* @param None
* @retval Unique number, used as a random seed
*/
uint32_t HW_GetRandomSeed(void);
/**
* @brief Gets the board 64 bits unique ID
* @param Pointer to an array that will contain the Unique ID
* @retval None
*/
void HW_GetUniqueId(uint8_t *id);
/**
* @brief Enters Low Power Stop Mode
* @note ARM exists the function when waking up
* @param None
* @retval None
*/
void HW_EnterStopMode(void);
/**
* @brief Exit Low Power Stop Mode
* @note Enable the pll at 32MHz
* @param None
* @retval None
*/
void HW_ExitStopMode(void);
/**
* @brief Enters Low Power Sleep Mode
* @note ARM exists the function when waking up
* @param None
* @retval None
*/
void HW_EnterSleepMode(void);
/**
* @brief Configures the sytem Clock at start-up, as follow :
* System Clock source = PLL (HSI)
* SYSCLK(Hz) = 32000000
* HCLK(Hz) = 32000000
* AHB Prescaler = 1
* APB1 Prescaler = 1
* APB2 Prescaler = 1
* HSI Frequency(Hz) = 16000000
* PLLMUL = 6
* PLLDIV = 3
* Flash Latency(WS) = 1
* @param None
* @retval None
*/
void SystemClock_Config(void);
/**
* @brief Configure all GPIO's to Analog input to reduce the power consumption
* @param None
* @retval None
*/
void HW_GpioInit(void);
void SYS_LED_OFF(void);
void SYS_LED_ON(void);
#ifdef __cplusplus
}
#endif
#endif /* __HW_MSP_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: Bleeper board GPIO driver implementation
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file hw_rtc.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief Header for driver hw_rtc.c module
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HW_RTC_H__
#define __HW_RTC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "utilities.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @brief Initializes the RTC timer
* @note The timer is based on the RTC
* @param None
* @retval None
*/
void HW_RTC_Init(void);
/**
* @brief Stop the Alarm
* @param None
* @retval None
*/
void HW_RTC_StopAlarm(void);
/**
* @brief Return the minimum timeout the RTC is able to handle
* @param None
* @retval Minimum value for a timeout
*/
uint32_t HW_RTC_GetMinimumTimeout(void);
/**
* @brief Set the alarm
* @note The alarm is set at now (read in this funtion) + timeout
* @param Timeout Duration of the Timer ticks
* @retval None
*/
void HW_RTC_SetAlarm(uint32_t timeout);
/**
* @brief Get the RTC timer elapsed time since the last Alarm was set
* @param None
* @retval RTC Elapsed time in ticks
*/
uint32_t HW_RTC_GetTimerElapsedTime(void);
/**
* @brief Get the RTC timer value
* @param None
* @retval RTC Timer value in ticks
*/
uint32_t HW_RTC_GetTimerValue(void);
/**
* @brief Set the RTC timer Reference
* @param None
* @retval Timer Reference Value in Ticks
*/
uint32_t HW_RTC_SetTimerContext(void);
/**
* @brief Get the RTC timer Reference
* @param None
* @retval Timer Value in Ticks
*/
uint32_t HW_RTC_GetTimerContext(void);
/**
* @brief RTC IRQ Handler on the RTC Alarm
* @param None
* @retval None
*/
void HW_RTC_IrqHandler(void);
/**
* @brief Delay of delay ms by polling RTC
* @param Delay in ms
* @retval None
*/
void HW_RTC_DelayMs(uint32_t delay);
/**
* @brief Calculates the wake up time between wake up and mcu start
* @note Resolution in RTC_ALARM_TIME_BASE
* @param None
* @retval None
*/
void HW_RTC_setMcuWakeUpTime(void);
/**
* @brief Converts time in ms to time in ticks
* @param Time in milliseconds
* @retval Returns time in timer ticks
*/
uint32_t HW_RTC_ms2Tick(TimerTime_t timeMicroSec);
/**
* @brief Converts time in ticks to time in ms
* @param Time in timer ticks
* @retval Time in timer milliseconds
*/
TimerTime_t HW_RTC_Tick2ms(uint32_t tick);
#ifdef __cplusplus
}
#endif
#endif /* __HW_RTC_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: Header for driver hw spi module
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file hw_spi.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief Header for driver hw_spi.c module
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HW_SPI_H__
#define __HW_SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hw_conf.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @brief Initializes the SPI object and MCU peripheral
*
* @param [IN] None
* @retval None
*/
void HW_SPI_Init(void);
/**
* @brief De-initializes the SPI object and MCU peripheral
*
* @param [IN] None
* @retval None
*/
void HW_SPI_DeInit(void);
/**
* @brief Initializes the SPI IOs
*
* @param [IN] None
* @retval None
*/
void HW_SPI_IoInit(void);
/**
* @brief De-initializes the SPI IOs
*
* @param [IN] None
* @retval None
*/
void HW_SPI_IoDeInit(void);
/**
* @brief Sends outData and receives inData
*
* @param [IN] outData Byte to be sent
* @retval inData Received byte.
* @note This is an implementation of
* HAL_SPI_TransmitReceive(&hspi, (uint8_t *)&txData, (uint8_t*)&rxData, 1, HAL_MAX_DELAY);
*/
uint16_t HW_SPI_InOut(uint16_t outData);
#ifdef __cplusplus
}
#endif
#endif /* __HW_SPI_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: LoRaMac classA device implementation
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis, Gregory Cristian and Wael Guibene
*/
/******************************************************************************
* @file lora.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief lora API to drive the lora state Machine
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __LORA_MAIN_H__
#define __LORA_MAIN_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "Comissioning.h"
#include "LoRaMac.h"
#include "region/Region.h"
/* Exported constants --------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/*!
* Application Data structure
*/
typedef struct
{
/*point to the LoRa App data buffer*/
uint8_t* Buff;
/*LoRa App data buffer size*/
uint8_t BuffSize;
/*Port on which the LoRa App is data is sent/ received*/
uint8_t Port;
} lora_AppData_t;
/*!
* LoRa State Machine states
*/
typedef enum eDevicState
{
DEVICE_STATE_INIT,
DEVICE_STATE_JOIN,
DEVICE_STATE_JOINED,
DEVICE_STATE_SEND,
DEVICE_STATE_CYCLE,
DEVICE_STATE_SLEEP
} DeviceState_t;
/*!
* LoRa State Machine states
*/
typedef enum eTxEventType
{
/*!
* @brief AppdataTransmition issue based on timer every TxDutyCycleTime
*/
TX_ON_TIMER,
/*!
* @brief AppdataTransmition external event plugged on OnSendEvent( )
*/
TX_ON_EVENT
} TxEventType_t;
/*!
* LoRa State Machine states
*/
typedef struct sLoRaParam
{
/*!
* @brief Event type
*
* @retval value battery level ( 0: very low, 254: fully charged )
*/
TxEventType_t TxEvent;
/*!
* @brief Application data transmission duty cycle in ms
*
* @note when TX_ON_TIMER Event type is selected
*/
uint32_t TxDutyCycleTime;
/*!
* @brief LoRaWAN device class
*/
DeviceClass_t Class;
/*!
* @brief Activation state of adaptativeDatarate
*/
bool AdrEnable;
/*!
* @brief Uplink datarate, if AdrEnable is off
*/
int8_t TxDatarate;
/*!
* @brief Enable or disable a public network
*
*/
bool EnablePublicNetwork;
/*!
* @brief Number of trials for the join request.
*/
uint8_t NbTrials;
} LoRaParam_t;
/* Lora Main callbacks*/
typedef struct sLoRaMainCallback
{
/*!
* @brief Get the current battery level
*
* @retval value battery level ( 0: very low, 254: fully charged )
*/
uint8_t ( *BoardGetBatteryLevel )( void );
/*!
* @brief Gets the board 64 bits unique ID
*
* @param [IN] id Pointer to an array that will contain the Unique ID
*/
void ( *BoardGetUniqueId ) ( uint8_t *id);
/*!
* Returns a pseudo random seed generated using the MCU Unique ID
*
* @retval seed Generated pseudo random seed
*/
uint32_t ( *BoardGetRandomSeed ) (void);
/*!
* @brief Prepares Tx Data to be sent on Lora network
*
* @param [IN] AppData is a buffer to fill
*
* @param [IN] port is a Application port on wicth Appdata will be sent
*
* @param [IN] length of the AppDataBuffer to send
*
* @param [IN] requests a confirmed Frame from the Network
*/
void ( *LoraTxData ) ( lora_AppData_t *AppData, FunctionalState* IsTxConfirmed);
/*!
* @brief Process Rx Data received from Lora network
*
* @param [IN] AppData is a buffer to process
*
* @param [IN] port is a Application port on wicth Appdata will be sent
*
* @param [IN] length is the number of recieved bytes
*/
void ( *LoraRxData ) ( lora_AppData_t *AppData);
} LoRaMainCallback_t;
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @brief Lora Initialisation
* @param [IN] LoRaMainCallback_t
* @param [IN] application parmaters
* @retval none
*/
void lora_Init (LoRaMainCallback_t *callbacks, LoRaParam_t* LoRaParam );
/**
* @brief run Lora classA state Machine
* @param [IN] none
* @retval none
*/
void lora_fsm( void );
/**
* @brief functionl requesting loRa state machine to send data
* @note function to link in mode TX_ON_EVENT
* @param none
* @retval none
*/
void OnSendEvent( void );
/**
* @brief API returns the state of the lora state machine
* @note return @DeviceState_t state
* @param [IN] none
* @retval return @FlagStatus
*/
DeviceState_t lora_getDeviceState( void );
#ifdef __cplusplus
}
#endif
#endif /*__LORA_MAIN_H__*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __LORAWAN_PORT_H__
#define __LORAWAN_PORT_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <string.h>
#include <stdio.h>
#include "hal/lorawan.h"
#include "utilities.h"
#include <k_api.h>
typedef uint32_t time_ms_t;
typedef uint32_t time_tick_t;
extern hal_lrwan_dev_chg_mode_t aos_lrwan_chg_mode;
extern hal_lrwan_time_itf_t aos_lrwan_time_itf;
extern hal_lrwan_radio_ctrl_t aos_lrwan_radio_ctrl;
#ifdef __cplusplus
}
#endif
#endif /* lorawan_port.h */

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/**
******************************************************************************
* @file stm32l0xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0xx_HAL_CONF_H__
#define __STM32L0xx_HAL_CONF_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32l0xx_hal_def.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
/* #define HAL_COMP_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
#define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LCD_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
/* #define HAL_RNG_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
/* #define HAL_TIM_MODULE_ENABLED */
/* #define HAL_TSC_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
#define HAL_CORTEX_MODULE_ENABLED
/* #define HAL_PCD_MODULE_ENABLED */
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
*
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /**< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /**< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal Multiple Speed oscillator (MSI) default value.
*
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /**< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
*
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /**< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /**< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)37000) /**< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /**< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
*
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /**< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /**< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /**< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1 << __NVIC_PRIO_BITS) - 1) /**< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define PREREAD_ENABLE 0
#define BUFFER_CACHE_DISABLE 0
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32l0xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32l0xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32l0xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32l0xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32l0xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32l0xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32l0xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32l0xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32l0xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32l0xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32l0xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32l0xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32l0xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED
#include "stm32l0xx_hal_lcd.h"
#endif /* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32l0xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32l0xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32l0xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32l0xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32l0xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32l0xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32l0xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32l0xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32l0xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32l0xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32l0xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32l0xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32l0xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32l0xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L0xx_HAL_CONF_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -0,0 +1,162 @@
/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: virtual com port driver
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/******************************************************************************
* @file vcom.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief Header for vcom.c module
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __VCOM_H__
#define __VCOM_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "hw_conf.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* External variables --------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @brief Init the VCOM.
* @param None
* @retval None
*/
void vcom_Init(void);
/**
* @brief DeInit the VCOM.
* @param None
* @retval None
*/
void vcom_DeInit(void);
/**
* @brief Init the VCOM IOs.
* @param None
* @retval None
*/
void vcom_IoInit(void);
/**
* @brief Init the VCOM RX
* @param None
* @retval None
*/
void vcom_ReceiveInit(void);
/**
* @brief DeInit the VCOM IOs.
* @param None
* @retval None
*/
void vcom_IoDeInit(void);
/**
* @brief Sends string on com port
* @param String
* @retval None
*/
void vcom_Send(const char *format, ...);
/**
* @brief Checks if a new character has been received on com port
* @param None
* @retval Returns SET if new character has been received on com port, RESET otherwise
*/
FlagStatus IsNewCharReceived(void);
/**
* @brief Gets new received characters on com port
* @param None
* @retval Returns the character
*/
uint8_t GetNewChar(void);
/**
* @brief vcom IRQ Handler
* @param None
* @retval None
*/
void vcom_IRQHandler(void);
void DBG_Send(const char *format, ...);
void DBG_Uart_Init(void);
void DBG_Uart_Deinit(void);
/* Exported macros -----------------------------------------------------------*/
#if 1
#include "debug.h"
#define PRINTF_RAW(...) DBG_Send(__VA_ARGS__)
#define PRINTF DBG_PRINTF
#else
#define PRINTF_RAW(...)
#define PRINTF(...)
#endif
#ifdef __cplusplus
}
#endif
#endif /* __VCOM_H__*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: LoRaMac classA device implementation
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis, Gregory Cristian and Wael Guibene
*/
/******************************************************************************
* @file version.h
* @author MCD Application Team
* @version V1.1.1
* @date 01-June-2017
* @brief defines the lora mac version
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __VERSION_H__
#define __VERSION_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#define LORA_MAC_VERSION (uint32_t) 0x44020000
/* Exported constants --------------------------------------------------------*/
#define TEST_VERSION (uint32_t) 0x00000000 /*1 lsb is always 0 in releases */
#define LRWAN_VERSION (uint32_t) 0x00001110 /*3 next hex is i_cube release*/
#define VERSION (uint32_t) (LORA_MAC_VERSION | LRWAN_VERSION | TEST_VERSION)
#define AT_VERSION_STRING "3.1.3"
#define AT_VERSION_LORAWAN_STRING "1.0.2"
/* Exported types ------------------------------------------------------------*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#ifdef __cplusplus
}
#endif
#endif /*__VERSION_H__*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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