mirror of
https://github.com/Ai-Thinker-Open/Ai-Thinker-Open_RTL8710BX_ALIOS_SDK.git
synced 2025-03-19 19:22:55 +00:00
391 lines
16 KiB
C
391 lines
16 KiB
C
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#include "hal/soc/soc.h"
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#include <aos/kernel.h>
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/* Logic partition on flash devices */
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hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX];
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void board_init(void)
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{
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hal_partitions[HAL_PARTITION_BOOTLOADER].partition_owner = HAL_FLASH_EMBEDDED;
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hal_partitions[HAL_PARTITION_BOOTLOADER].partition_description = "Bootloader";
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hal_partitions[HAL_PARTITION_BOOTLOADER].partition_start_addr = 0x08000000;
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hal_partitions[HAL_PARTITION_BOOTLOADER].partition_length = 0x8000; //500k bytes
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hal_partitions[HAL_PARTITION_BOOTLOADER].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS;
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hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = HAL_FLASH_EMBEDDED;
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hal_partitions[HAL_PARTITION_APPLICATION].partition_description = "Application";
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hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = 0x08008000;
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hal_partitions[HAL_PARTITION_APPLICATION].partition_length = 0x98000; //608K bytes
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hal_partitions[HAL_PARTITION_APPLICATION].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
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hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_owner = HAL_FLASH_QSPI;
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hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_description = "RF Firmware";
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hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_start_addr = 0x2000;
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hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_length = 0x3E000; // 4k bytes
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hal_partitions[HAL_PARTITION_RF_FIRMWARE].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
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hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = HAL_FLASH_QSPI;
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hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = "PARAMETER1";
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hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = 0x0;
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hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = 0x2000; // 8k bytes
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hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
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hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = HAL_FLASH_QSPI;
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hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = "PARAMETER2";
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hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = 0xDA000;
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hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = 0x2000; //8k bytes
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hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
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hal_partitions[HAL_PARTITION_OTA_TEMP].partition_owner = HAL_FLASH_EMBEDDED;
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hal_partitions[HAL_PARTITION_OTA_TEMP].partition_description = "OTA Storage";
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hal_partitions[HAL_PARTITION_OTA_TEMP].partition_start_addr = 0x40000;
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hal_partitions[HAL_PARTITION_OTA_TEMP].partition_length = 0x98000; //608K bytes
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hal_partitions[HAL_PARTITION_OTA_TEMP].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
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hal_partitions[HAL_PARTITION_PARAMETER_3].partition_owner = HAL_FLASH_QSPI;
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hal_partitions[HAL_PARTITION_PARAMETER_3].partition_description = "PARAMETER3";
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hal_partitions[HAL_PARTITION_PARAMETER_3].partition_start_addr = 0xD8000;
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hal_partitions[HAL_PARTITION_PARAMETER_3].partition_length = 0x1000; //4k bytes
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hal_partitions[HAL_PARTITION_PARAMETER_3].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
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hal_partitions[HAL_PARTITION_PARAMETER_4].partition_owner = HAL_FLASH_QSPI;
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hal_partitions[HAL_PARTITION_PARAMETER_4].partition_description = "PARAMETER4";
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hal_partitions[HAL_PARTITION_PARAMETER_4].partition_start_addr = 0xD9000;
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hal_partitions[HAL_PARTITION_PARAMETER_4].partition_length = 0x1000; //4k bytes
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hal_partitions[HAL_PARTITION_PARAMETER_4].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN;
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}
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#include "platform_config.h"
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#include "platform_peripheral.h"
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#include "platform_config.h"
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#include "platform_logging.h"
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#include "wlan_platform_common.h"
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/******************************************************
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* Function Declarations
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******************************************************/
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extern WEAK void PlatformEasyLinkButtonClickedCallback(void);
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extern WEAK void PlatformEasyLinkButtonLongPressedCallback(void);
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extern WEAK void bootloader_start(void);
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/******************************************************
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* Variables Definitions
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******************************************************/
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const platform_gpio_t platform_gpio_pins[] =
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{
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/* Common GPIOs for internal use */
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[FLASH_PIN_QSPI_CS ] = { GPIOC, 11 },
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[FLASH_PIN_QSPI_CLK] = { GPIOB, 1 },
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[FLASH_PIN_QSPI_D0] = { GPIOA, 6 },
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[FLASH_PIN_QSPI_D1] = { GPIOA, 7 },
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[FLASH_PIN_QSPI_D2] = { GPIOC, 4 },
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[FLASH_PIN_QSPI_D3] = { GPIOC, 5 },
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/* GPIOs for external use */
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[MICO_GPIO_2] = { GPIOB, 2 },
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[MICO_GPIO_4] = { GPIOB, 15 },
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[MICO_GPIO_5] = { GPIOB, 12 },
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[MICO_GPIO_6] = { GPIOB, 13 },
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[MICO_GPIO_7] = { GPIOB, 14 },
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[MICO_GPIO_8] = { GPIOC, 6 },
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[MICO_GPIO_9] = { GPIOA, 15 },
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[MICO_GPIO_12] = { GPIOC, 7 },
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[MICO_GPIO_14] = { GPIOC, 0 },
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[MICO_GPIO_16] = { GPIOC, 13 },
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[MICO_GPIO_17] = { GPIOB, 8 },
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[MICO_GPIO_18] = { GPIOB, 9 },
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[MICO_GPIO_19] = { GPIOB, 10 },
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[MICO_GPIO_27] = { GPIOB, 3 },
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[MICO_GPIO_29] = { GPIOB, 7 },
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[MICO_GPIO_30] = { GPIOB, 6 },
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[MICO_GPIO_31] = { GPIOB, 4 },
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[MICO_GPIO_33] = { GPIOA, 10 },
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[MICO_GPIO_34] = { GPIOA, 5 },
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[MICO_GPIO_35] = { GPIOA, 11 },
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[MICO_GPIO_36] = { GPIOA, 12 },
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[MICO_GPIO_37] = { GPIOB, 0 },
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[MICO_GPIO_38] = { GPIOA, 4 },
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};
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const platform_pwm_t *platform_pwm_peripherals = NULL;
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const platform_i2c_t platform_i2c_peripherals[] =
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{
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[MICO_I2C_1] =
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{
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.port = I2C1,
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.pin_scl = &platform_gpio_pins[MICO_GPIO_17],
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.pin_sda = &platform_gpio_pins[MICO_GPIO_18],
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.peripheral_clock_reg = RCC_APB1Periph_I2C1,
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.tx_dma = DMA1,
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.tx_dma_peripheral_clock = RCC_AHB1Periph_DMA1,
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.tx_dma_stream = DMA1_Stream7,
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.rx_dma_stream = DMA1_Stream5,
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.tx_dma_stream_id = 7,
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.rx_dma_stream_id = 5,
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.tx_dma_channel = DMA_Channel_1,
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.rx_dma_channel = DMA_Channel_1,
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.gpio_af_scl = GPIO_AF_I2C1,
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.gpio_af_sda = GPIO_AF_I2C1
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},
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};
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platform_i2c_driver_t platform_i2c_drivers[MICO_I2C_MAX];
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const platform_uart_t platform_uart_peripherals[] =
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{
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[MICO_UART_1] =
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{
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.port = USART6,
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.pin_tx = &platform_gpio_pins[MICO_GPIO_8],
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.pin_rx = &platform_gpio_pins[MICO_GPIO_12],
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.pin_cts = NULL,
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.pin_rts = NULL,
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.tx_dma_config =
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{
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.controller = DMA2,
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.stream = DMA2_Stream6,
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.channel = DMA_Channel_5,
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.irq_vector = DMA2_Stream6_IRQn,
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.complete_flags = DMA_HISR_TCIF6,
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.error_flags = ( DMA_HISR_TEIF6 | DMA_HISR_FEIF6 ),
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},
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.rx_dma_config =
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{
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.controller = DMA2,
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.stream = DMA2_Stream1,
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.channel = DMA_Channel_5,
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.irq_vector = DMA2_Stream1_IRQn,
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.complete_flags = DMA_LISR_TCIF1,
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.error_flags = ( DMA_LISR_TEIF1 | DMA_LISR_FEIF1 | DMA_LISR_DMEIF1 ),
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},
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},
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[MICO_UART_2] =
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{
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.port = USART1,
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.pin_tx = &platform_gpio_pins[MICO_GPIO_30],
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.pin_rx = &platform_gpio_pins[MICO_GPIO_29],
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.pin_cts = NULL,
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.pin_rts = NULL,
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.tx_dma_config =
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{
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.controller = DMA2,
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.stream = DMA2_Stream7,
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.channel = DMA_Channel_4,
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.irq_vector = DMA2_Stream7_IRQn,
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.complete_flags = DMA_HISR_TCIF7,
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.error_flags = ( DMA_HISR_TEIF7 | DMA_HISR_FEIF7 ),
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},
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.rx_dma_config =
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{
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.controller = DMA2,
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.stream = DMA2_Stream2,
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.channel = DMA_Channel_4,
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.irq_vector = DMA2_Stream2_IRQn,
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.complete_flags = DMA_LISR_TCIF2,
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.error_flags = ( DMA_LISR_TEIF2 | DMA_LISR_FEIF2 | DMA_LISR_DMEIF2 ),
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},
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},
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};
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platform_uart_driver_t platform_uart_drivers[MICO_UART_MAX];
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const platform_spi_t platform_spi_peripherals[] =
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{
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[MICO_SPI_1] =
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{
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.port = SPI2,
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.gpio_af = GPIO_AF_SPI2,
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.peripheral_clock_reg = RCC_APB1Periph_SPI2,
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.peripheral_clock_func = RCC_APB1PeriphClockCmd,
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.pin_mosi = &platform_gpio_pins[MICO_GPIO_4],
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.pin_miso = &platform_gpio_pins[MICO_GPIO_7],
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.pin_clock = &platform_gpio_pins[MICO_GPIO_6],
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.tx_dma =
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{
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.controller = DMA1,
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.stream = DMA1_Stream4,
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.channel = DMA_Channel_0,
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.irq_vector = DMA1_Stream4_IRQn,
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.complete_flags = DMA_HISR_TCIF4,
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.error_flags = ( DMA_HISR_TEIF4 | DMA_HISR_FEIF4 ),
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},
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.rx_dma =
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{
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.controller = DMA1,
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.stream = DMA1_Stream3,
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.channel = DMA_Channel_0,
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.irq_vector = DMA1_Stream3_IRQn,
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.complete_flags = DMA_LISR_TCIF3,
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.error_flags = ( DMA_LISR_TEIF3 | DMA_LISR_FEIF3 | DMA_LISR_DMEIF3 ),
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},
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}
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};
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platform_spi_driver_t platform_spi_drivers[MICO_SPI_MAX];
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const platform_qspi_t platform_qspi_peripherals[] =
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{
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[MICO_QSPI_1] =
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{
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.port = QUADSPI,
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.FSelect = QSPI_FSelect_2,
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.peripheral_clock_reg = RCC_AHB3Periph_QSPI,
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.peripheral_clock_func = RCC_AHB3PeriphClockCmd,
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.pin_d0 = &platform_gpio_pins[FLASH_PIN_QSPI_D0],
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.pin_d1 = &platform_gpio_pins[FLASH_PIN_QSPI_D1],
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.pin_d2 = &platform_gpio_pins[FLASH_PIN_QSPI_D2],
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.pin_d3 = &platform_gpio_pins[FLASH_PIN_QSPI_D3],
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.pin_clock = &platform_gpio_pins[FLASH_PIN_QSPI_CLK],
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.pin_cs = &platform_gpio_pins[FLASH_PIN_QSPI_CS],
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#ifdef USE_QUAD_SPI_DMA
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.dma =
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{
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.controller = DMA2,
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.stream = DMA2_Stream7,
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.channel = DMA_Channel_3,
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.complete_flags = DMA_FLAG_TCIF7,
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},
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#endif
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.gpio_af_d0 = GPIO_AF10_QUADSPI,
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.gpio_af_d1 = GPIO_AF10_QUADSPI,
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.gpio_af_d2 = GPIO_AF10_QUADSPI,
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.gpio_af_d3 = GPIO_AF10_QUADSPI,
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.gpio_af_clk = GPIO_AF9_QUADSPI,
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.gpio_af_cs = GPIO_AF9_QUADSPI,
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}
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};
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//platform_qspi_driver_t platform_qspi_drivers[MICO_QSPI_MAX];
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/* Flash memory devices */
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const platform_flash_t platform_flash_peripherals[] =
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{
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[HAL_FLASH_EMBEDDED] =
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{
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.flash_type = FLASH_TYPE_EMBEDDED,
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.flash_start_addr = 0x08000000,
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.flash_length = 0x100000,
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},
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[HAL_FLASH_QSPI] =
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{
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.flash_type = FLASH_TYPE_QSPI,
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.flash_start_addr = 0x000000,
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.flash_length = 0x200000,
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},
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};
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platform_flash_driver_t platform_flash_drivers[HAL_FLASH_MAX];
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#if defined ( USE_MICO_SPI_FLASH )
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const mico_spi_device_t mico_spi_flash =
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{
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.port = MICO_SPI_1,
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.chip_select = FLASH_PIN_SPI_CS,
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.speed = 40000000,
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.mode = (SPI_CLOCK_RISING_EDGE | SPI_CLOCK_IDLE_HIGH | SPI_USE_DMA | SPI_MSB_FIRST ),
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.bits = 8
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};
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#endif
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const platform_adc_t platform_adc_peripherals[] =
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{
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[MICO_ADC_1] = { ADC1, ADC_Channel_4, RCC_APB2Periph_ADC1, 1, (platform_gpio_t*)&platform_gpio_pins[MICO_GPIO_38] },
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[MICO_ADC_2] = { ADC1, ADC_Channel_5, RCC_APB2Periph_ADC1, 1, (platform_gpio_t*)&platform_gpio_pins[MICO_GPIO_34] },
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};
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/* Wi-Fi control pins. Used by platform/MCU/wlan_platform_common.c
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* SDIO: EMW1062_PIN_BOOTSTRAP[1:0] = b'00
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* gSPI: EMW1062_PIN_BOOTSTRAP[1:0] = b'01
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*/
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const platform_gpio_t wifi_control_pins[] =
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{
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[WIFI_PIN_RESET] = { GPIOA, 9 },
|
||
|
|
[WIFI_PIN_32K_CLK] = { GPIOA, 8 },
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Wi-Fi SDIO bus pins. Used by platform/MCU/STM32F2xx/EMW1062_driver/wlan_SDIO.c */
|
||
|
|
const platform_gpio_t wifi_sdio_pins[] =
|
||
|
|
{
|
||
|
|
[WIFI_PIN_SDIO_OOB_IRQ] = { GPIOC, 0 },
|
||
|
|
[WIFI_PIN_SDIO_CLK ] = { GPIOC, 12 },
|
||
|
|
[WIFI_PIN_SDIO_CMD ] = { GPIOD, 2 },
|
||
|
|
[WIFI_PIN_SDIO_D0 ] = { GPIOC, 8 },
|
||
|
|
[WIFI_PIN_SDIO_D1 ] = { GPIOC, 9 },
|
||
|
|
[WIFI_PIN_SDIO_D2 ] = { GPIOC, 10 },
|
||
|
|
[WIFI_PIN_SDIO_D3 ] = { GPIOB, 5 },
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
/******************************************************
|
||
|
|
* Interrupt Handler Definitions
|
||
|
|
******************************************************/
|
||
|
|
|
||
|
|
MICO_RTOS_DEFINE_ISR( USART1_IRQHandler )
|
||
|
|
{
|
||
|
|
platform_uart_irq( &platform_uart_drivers[MICO_UART_2] );
|
||
|
|
}
|
||
|
|
|
||
|
|
MICO_RTOS_DEFINE_ISR( USART6_IRQHandler )
|
||
|
|
{
|
||
|
|
platform_uart_irq( &platform_uart_drivers[MICO_UART_1] );
|
||
|
|
}
|
||
|
|
|
||
|
|
MICO_RTOS_DEFINE_ISR( DMA2_Stream6_IRQHandler )
|
||
|
|
{
|
||
|
|
platform_uart_tx_dma_irq( &platform_uart_drivers[MICO_UART_1] );
|
||
|
|
}
|
||
|
|
|
||
|
|
MICO_RTOS_DEFINE_ISR( DMA2_Stream7_IRQHandler )
|
||
|
|
{
|
||
|
|
platform_uart_tx_dma_irq( &platform_uart_drivers[MICO_UART_2] );
|
||
|
|
}
|
||
|
|
|
||
|
|
MICO_RTOS_DEFINE_ISR( DMA2_Stream1_IRQHandler )
|
||
|
|
{
|
||
|
|
platform_uart_rx_dma_irq( &platform_uart_drivers[MICO_UART_1] );
|
||
|
|
}
|
||
|
|
|
||
|
|
MICO_RTOS_DEFINE_ISR( DMA2_Stream2_IRQHandler )
|
||
|
|
{
|
||
|
|
platform_uart_rx_dma_irq( &platform_uart_drivers[MICO_UART_2] );
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/******************************************************
|
||
|
|
* Function Definitions
|
||
|
|
******************************************************/
|
||
|
|
|
||
|
|
void platform_init_peripheral_irq_priorities( void )
|
||
|
|
{
|
||
|
|
/* Interrupt priority setup. Called by MiCO/platform/MCU/STM32F4xx/platform_init.c */
|
||
|
|
NVIC_SetPriority( RTC_WKUP_IRQn , 1 ); /* RTC Wake-up event */
|
||
|
|
NVIC_SetPriority( SDIO_IRQn , 2 ); /* WLAN SDIO */
|
||
|
|
NVIC_SetPriority( DMA2_Stream3_IRQn, 3 ); /* WLAN SDIO DMA */
|
||
|
|
//NVIC_SetPriority( DMA1_Stream3_IRQn, 3 ); /* WLAN SPI DMA */
|
||
|
|
NVIC_SetPriority( USART6_IRQn , 6 ); /* MICO_UART_1 */
|
||
|
|
NVIC_SetPriority( USART1_IRQn , 6 ); /* MICO_UART_2 */
|
||
|
|
NVIC_SetPriority( DMA2_Stream6_IRQn, 7 ); /* MICO_UART_1 TX DMA */
|
||
|
|
NVIC_SetPriority( DMA2_Stream1_IRQn, 7 ); /* MICO_UART_1 RX DMA */
|
||
|
|
NVIC_SetPriority( DMA2_Stream7_IRQn, 7 ); /* MICO_UART_2 TX DMA */
|
||
|
|
NVIC_SetPriority( DMA2_Stream2_IRQn, 7 ); /* MICO_UART_2 RX DMA */
|
||
|
|
NVIC_SetPriority( EXTI0_IRQn , 14 ); /* GPIO */
|
||
|
|
NVIC_SetPriority( EXTI1_IRQn , 14 ); /* GPIO */
|
||
|
|
NVIC_SetPriority( EXTI2_IRQn , 14 ); /* GPIO */
|
||
|
|
NVIC_SetPriority( EXTI3_IRQn , 14 ); /* GPIO */
|
||
|
|
NVIC_SetPriority( EXTI4_IRQn , 14 ); /* GPIO */
|
||
|
|
NVIC_SetPriority( EXTI9_5_IRQn , 14 ); /* GPIO */
|
||
|
|
NVIC_SetPriority( EXTI15_10_IRQn , 14 ); /* GPIO */
|
||
|
|
}
|
||
|
|
|
||
|
|
void init_platform( void )
|
||
|
|
{
|
||
|
|
|
||
|
|
}
|
||
|
|
|